RC28F256P30TFB Micron Technology Inc, RC28F256P30TFB Datasheet - Page 27

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RC28F256P30TFB

Manufacturer Part Number
RC28F256P30TFB
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of RC28F256P30TFB

Cell Type
NOR
Density
256Mb
Access Time (max)
100ns
Interface Type
Parallel/Serial
Boot Type
Top
Address Bus
24b
Operating Supply Voltage (typ)
1.8V
Operating Temp Range
-40C to 85C
Package Type
EZBGA
Sync/async
Async/Sync
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
1.7V
Operating Supply Voltage (max)
2V
Word Size
16b
Number Of Words
16M
Supply Current
31mA
Mounting
Surface Mount
Pin Count
64
Lead Free Status / Rohs Status
Not Compliant

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Part Number:
RC28F256P30TFB
Quantity:
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P30-65nm
8.0
8.1
8.2
Datasheet
27
Program Operation
The device supports three programming methods: Word Programming (40h or 10h),
Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h,
D0h). See
programming commands issued to the device. The following sections describe device
programming in detail.
Successful programming requires the addressed block to be unlocked. If the block is
locked down, WP# must be deasserted and the block must be unlocked before
attempting to program the block. Attempting to program a locked block causes a
program error (SR.4 and SR.1 set) and termination of the operation. See
“Security Modes” on page 35
Word Programming
Word programming operations are initiated by writing the Word Program Setup
command to the device (see
followed by a second write to the device with the address and data to be programmed.
The device outputs Status Register data when read. See
Flowchart” on page
max values.
During programming, the Write State Machine (WSM) executes a sequence of
internally-timed events that program the desired data bits at the addressed location,
and verifies that the bits are sufficiently programmed. Programming the flash memory
array changes “ones” to “zeros”. Memory array bits that are zeros can be changed to
ones only by erasing the block (see
The Status Register can be examined for programming progress and errors by reading
at any address. The device remains in the Read Status Register state until another
command is written to the device.
Status Register bit SR.7 indicates the programming status while the sequence
executes. Commands that can be issued to the device during programming are
Program Suspend, Read Status Register, Read Device Identifier, Read CFI, and Read
Array (this returns unknown data).
When programming has finished, Status Register bit SR.4 (when set) indicates a
programming failure. If SR.3 is set, the WSM could not perform the word programming
operation because V
programming operation attempted to program a locked block, causing the operation to
abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow,
when word programming has completed.
Buffered Programming
The device features a 512-word buffer to enable optimum programming performance.
For Buffered Programming, data is first written to an on-chip write buffer. Then the
buffer data is programmed into the flash memory array in buffer-size increments. This
can improve system programming performance significantly over non-buffered
programming.
Section 5.0, “Bus Operations” on page 19
78. V
PP
was outside of its acceptable limits. If SR.1 is set, the word
PP
must be above V
Section 5.0, “Bus Operations” on page
for details on locking and unlocking blocks.
Section 9.0, “Erase Operations” on page
PPLK
, and within the specified V
for details on the various
Figure 35, “Word Program
Order Number: 320002-10
19). This is
Section 10.0,
PPL
33).
min/
Mar 2010

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