RC28F256P30TFB Micron Technology Inc, RC28F256P30TFB Datasheet - Page 75

• Manufacturer Part Number: RC28F256P30TFB
• Manufacturer: Micron Technology Inc

Specifications of RC28F256P30TFB

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 100ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 16M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

P30-65nm
Table 42: Partition Region 1 Information (continued)
Datasheet
75
Bottom
(P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information
(P+2C)h
(P+2D)h
(P+2E)h
(P+2F)h
(P+30)h
(P+31)h
(P+32)h
(P+33)h
(P+34)h
(P+35)h
(P+36)h
(P+37)h
(P+38)h
(P+39)h
(P+3B)h
(P+3C)h
(P+3D)h
(P+3E)h
(P+3F)h
(P+40)h
(P+41)h
(P+42)h
(P+43)h
(P+44)h
(P+45)h
(P+46)h
(P+47)h
P = 10Ah
Offset
(P+2C)h Partition Region 1 Erase Block Type 1 Information
(P+2D)h
(P+2E)h
(P+2F)h
(P+30)h Partition 1 (Erase Block Type 1)
(P+31)h
(P+32)h
(P+33)h
(P+34)h
(P+35)h
(P+36)h
(P+37)h
(P+38)h
(P+39)h
(P+3B)h
(P+3C)h
(P+3D)h
(P+3E)h Partition 1 (Erase Block Type 2)
(P+3F)h
(P+40)h
(P+41)h
(P+42)h
(P+43)h
(P+44)h
(P+45)h
(P+46)h
(P+47)h
(1)
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Partition 1 (erase block Type 1) bits per cell; internal EDAC
Partition 1 (erase block Type 1) page mode and synchronous mode capabilities
defined in Table 10.
Partition Region 1 (Erase Block Type 1) Programming Region Information
Partition 1 (erase block Type 2) bits per cell; internal EDAC
Partition 1 (erase block Type 2) page mode and synchronous mode capabilities
defined in Table 10.
Partition Region 1 (Erase Block Type 2) Programming Region Information
Block erase cycles x 1000
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitte
Block erase cycles x 1000
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitte
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
bits 0–7 = x, 2^x = Programming Region aligned size (bytes)
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16–23 = y = Control Mode valid size in bytes
bits 24-31 = Reserved
bits 32-39 = z = Control Mode invalid size in bytes
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
bits 0–7 = x, 2^x = Programming Region aligned size (bytes)
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16–23 = y = Control Mode valid size in bytes
bits 24-31 = Reserved
bits 32-39 = z = Control Mode invalid size in bytes
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
(Optional flash features and commands)
Description
Order Number: 320002-10
Len
4
2
1
1
6
4
2
1
1
6
See table below
13A:
14A:
136:
137:
138:
139:
13B:
13C:
13D:
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14B:
14C:
14D:
14E:
14F:
150:
151:
Bot
Address
Mar 2010
13A:
14A:
136:
137:
138:
139:
13B:
13C:
13D:
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14B:
14C:
14D:
14E:
14F:
150:
151:
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