MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 147
MC9S12C128VFU
Manufacturer Part Number
MC9S12C128VFU
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S12C128VFU.pdf
(690 pages)
Specifications of MC9S12C128VFU
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Interface Type
CAN/SCI/SPI
Program Memory Type
Flash
Program Memory Size
128KB
Total Internal Ram Size
4KB
# I/os (max)
60
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/2.97V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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4.3.2.12
Read: Anytime (provided this register is in the map)
Write: Refer to individual bit descriptions below
The EBICTL register is used to control miscellaneous functions (i.e., stretching of external E clock).
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
Freescale Semiconductor
Module Base + 0x000E
Starting address location affected by INITRG register setting.
All other modes
RDRK
RDPE
RDPB
RDPA
ESTR
Field
Field
Peripheral
7
4
1
0
0
Reset:
W
R
Reduced Drive of Port K
0 All port K output pins have full drive enabled.
1 All port K output pins have reduced drive enabled.
Reduced Drive of Port E
0 All port E output pins have full drive enabled.
1 All port E output pins have reduced drive enabled.
Reduced Drive of Port B
0 All port B output pins have full drive enabled.
1 All port B output pins have reduced drive enabled.
Reduced Drive of Ports A
0 All port A output pins have full drive enabled.
1 All port A output pins have reduced drive enabled.
E Clock Stretches — This control bit determines whether the E clock behaves as a simple free-running clock or
as a bus control signal that is active only for external bus cycles.
Normal and Emulation: write once
Special: write anytime
0 E never stretches (always free running).
1 E stretches high during stretched external accesses and remains low during non-visible internal accesses.
This bit has no effect in single-chip modes.
External Bus Interface Control Register (EBICTL)
7
0
0
0
Figure 4-16. External Bus Interface Control Register (EBICTL)
= Unimplemented or Reserved
6
0
0
0
Table 4-11. EBICTL Field Descriptions
Table 4-10. RDRIV Field Descriptions
MC9S12C-Family / MC9S12GC-Family
5
0
0
0
Rev 01.24
Description
0
0
0
Description
4
Chapter 4 Multiplexed External Bus Interface (MEBIV3)
0
0
0
3
0
0
0
2
0
0
0
1
ESTR
0
1
0
147
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