MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 95

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

2.3.2.4.5
Read: Anytime.
Write: Anytime.
2.3.2.4.6
Read: Anytime.
Write: Anytime.
Freescale Semiconductor
Module Base + 0x001C
Module Base + 0x001D
PERP[7:0]
PPSP[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
PERP7
PPSP7
Pull Device Enable Port P — This register configures whether a pull-up or a pull-down device is activated, if the
port is used as input. This bit has no effect if the port is used as output. Out of reset no pull device is enabled.
0 Pull-up or pull-down device is disabled.
1 Either a pull-up or pull-down device is enabled.
Pull Select Port P — This register serves a dual purpose by selecting the polarity of the active interrupt edge
as well as selecting a pull-up or pull-down device if enabled.
0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is
1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device
0
0
7
7
connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is
used as input.
Port P Pull Device Enable Register (PERP)
Port P Polarity Select Register (PPSP)
PERP6
PPSP6
Figure 2-28. Port P Pull Device Enable Register (PERP)
0
0
6
6
Figure 2-29. Port P Polarity Select Register (PPSP)
Table 2-24. PERP Field Descriptions
Table 2-25. PPSP Field Descriptions
PERP5
PPSP5
MC9S12C-Family / MC9S12GC-Family
0
0
5
5
PERP4
PPSP4
Rev 01.24
0
0
4
4
Description
Description
Chapter 2 Port Integration Module (PIM9C32) Block Description
PERP3
PPSP3
0
0
3
3
PERP2
PPSP2
0
0
2
2
PERP1
PPSP1
0
0
1
1
PERP0
PPSP0
0
0
0
0
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