MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 364

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
12.3.2.12 PWM Channel Counter Registers (PWMCNTx)
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source.
The counter can be read at any time without affecting the count or the operation of the PWM channel. In
left aligned output mode, the counter counts from 0 to the value in the period register – 1. In center aligned
output mode, the counter counts from 0 up to the value in the period register and then back down to 0.
Any value written to the counter causes the counter to reset to 0x0000, the counter direction to be set to
up, the immediate load of both duty and period registers with values from the buffers, and the output to
change according to the polarity bit. The counter is also cleared at the end of the effective period (see
Section 12.4.2.5, “Left Aligned Outputs,”
details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a
channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the
PWMCNTx register. For more detailed information on the operation of the counters, reference
Section 12.4.2.4, “PWM Timer Counters.”
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low- or
high-order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
364
Module Base + 0x000C
Module Base + 0x000D
Reset
Reset
W
W
R
R
Bit 7
Bit 7
0
0
0
0
7
7
Writing to the counter while the channel is enabled can cause an irregular
PWM cycle to occur.
Figure 12-15. PWM Channel Counter Registers (PWMCNT0)
Figure 12-16. PWM Channel Counter Registers (PWMCNT1)
6
0
0
6
0
0
6
6
MC9S12C-Family / MC9S12GC-Family
5
0
0
5
0
0
5
5
and
Section 12.4.2.6, “Center Aligned Outputs,”
Rev 01.24
NOTE
4
0
0
4
0
0
4
4
3
0
0
3
0
0
3
3
2
0
0
2
0
0
2
2
Freescale Semiconductor
1
0
0
1
0
0
1
1
for more
Bit 0
Bit 0
0
0
0
0
0
0