MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 173

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

6.3.2.2
Read: All modes
Write: All modes
When entering background debug mode, the BDM CCR holding register is used to save the contents of the
condition code register of the user’s program. It is also used for temporary storage in the standard BDM
firmware mode. The BDM CCR holding register can be written to modify the CCR value.
6.3.2.3
Read: All modes
Write: Never
Freescale Semiconductor
0xFF06
0xFF07
REG[14:11]
Reset
Reset
Field
6:3
W
W
R
R
CCR7
Internal Register Map Position — These four bits show the state of the upper five bits of the base address for
the system’s relocatable register block. BDMINR is a shadow of the INITRG register which maps the register
block to any 2K byte space within the first 32K bytes of the 64K byte address space.
BDM CCR Holding Register (BDMCCR)
BDM Internal Register Position Register (BDMINR)
0
0
0
7
7
When BDM is made active, the CPU stores the value of the CCR register in
the BDMCCR register. However, out of special single-chip reset, the
BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR
register.
= Unimplemented or Reserved
REG14
CCR6
0
0
6
6
Figure 6-5. BDM Internal Register Position (BDMINR)
Figure 6-4. BDM CCR Holding Register (BDMCCR)
Table 6-4. BDMINR Field Descriptions
REG13
CCR5
MC9S12C-Family / MC9S12GC-Family
0
0
5
5
REG12
CCR4
Rev 01.24
NOTE
0
0
4
4
Chapter 6 Background Debug Module (BDMV4) Block Description
Description
REG11
CCR3
0
0
3
3
CCR2
0
0
0
2
2
CCR1
0
0
0
1
1
CCR0
0
0
0
0
0
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