MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 263

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
* Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.
RTR[6:4]
RTR[3:0]
Field
1001 (÷10)
1010 (÷11)
1011 (÷12)
1100 (÷ 13)
1101 (÷14)
1110 (÷15)
1111 (÷ 16)
6:4
3:0
0000 (÷1)
0001 (÷2)
0010 (÷3)
0011 (÷4)
0100 (÷5)
0101 (÷6)
0110 (÷7)
0111 (÷8)
1000 (÷9)
RTR[3:0]
Real-Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See
Real-Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.
source clock for the RTI is OSCCLK.
(OFF)
OFF*
OFF*
OFF*
OFF*
OFF*
OFF*
OFF*
OFF*
OFF*
OFF*
OFF*
OFF*
OFF*
OFF*
OFF*
OFF*
000
10x2
11x2
12x2
13x2
14x2
15x2
16x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
(2
001
2
Table 9-7. RTI Frequency Divide Rates
Table 9-6. RTICTL Field Descriptions
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
)
MC9S12C-Family / MC9S12GC-Family
Table 9-7
10x2
11x2
12x2
13x2
14x2
15x2
16x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
(2
010
2
11
11
shows all possible divide values selectable by the RTICTL register. The
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
)
Rev 01.24
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Description
10x2
11x2
12x2
13x2
14x2
15x2
16x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
(2
011
2
12
12
RTR[6:4] =
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
)
10x2
11x2
12x2
13x2
14x2
15x2
16x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
(2
100
2
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
)
10x2
11x2
12x2
13x2
14x2
15x2
16x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
(2
101
2
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
)
10x2
11x2
12x2
13x2
14x2
15x2
16x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
(2
110
2
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
)
Table
10x2
11x2
12x2
13x2
14x2
15x2
16x2
2x2
3x2
4x2
5x2
6x2
7x2
8x2
9x2
(2
111
2
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
)
9-7.
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