MC9S12C128VFU Freescale Semiconductor, MC9S12C128VFU Datasheet - Page 277

• Manufacturer Part Number: MC9S12C128VFU
• Manufacturer: Freescale Semiconductor

Specifications of MC9S12C128VFU

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 25MHz
• Interface Type: CAN/SCI/SPI
• Program Memory Type: Flash
• Program Memory Size: 128KB
• Total Internal Ram Size: 4KB
• # I/os (max): 60
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
CME
0
1
1
SCME
X
0
1
SCMIE
X
X
0
Clock failure -->
Clock failure -->
Clock failure -->
Scenario 1: OSCCLK recovers prior to exiting Wait Mode.
– CM no longer indicates a failure,
Some time later either a wakeup interrupt occurs (no SCM interrupt)
or an External Reset is applied.
Scenario 2: OSCCLK does not recover prior to exiting Wait Mode.
Some time later either a wakeup interrupt occurs (no SCM interrupt)
No action, clock loss not detected.
CRG performs Clock Monitor Reset immediately
– MCU remains in Wait Mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start Clock Quality Check,
– Set SCMIF interrupt flag.
Some time later OSCCLK recovers.
– 4096 OSCCLK cycles later Clock Quality Check indicates clock o.k.,
– SCM deactivated,
– PLL disabled depending on PLLWAI,
– VREG remains enabled (never gets disabled in Wait Mode).
– MCU remains in Wait Mode.
– Exit Wait Mode using OSCCLK as system clock (SYSCLK),
– Continue normal operation.
– Exit Wait Mode using OSCCLK as system clock,
– Start reset sequence.
– MCU remains in Wait Mode,
– VREG enabled,
– PLL enabled,
– SCM activated,
– Start Clock Quality Check,
– Set SCMIF interrupt flag,
– Keep performing Clock Quality Checks (could continue infinitely)
– Exit Wait Mode in SCM using PLL clock (f
– Continue to perform additional Clock Quality Checks until OSCCLK
or an External RESET is applied.
– Exit Wait Mode in SCM using PLL clock (f
– Start reset sequence,
– Continue to perform additional Clock Quality Checks until OSCCLK
Table 9-11. Outcome of Clock Loss in Wait Mode
is o.k. again.
is o.k.again.
while in Wait Mode.
MC9S12C-Family / MC9S12GC-Family
Rev 01.24
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
CRG Actions
SCM
SCM
) as system clock,
) as system clock,
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