ISP1761BE STEricsson, ISP1761BE Datasheet - Page 103

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
ISP1761_5
Product data sheet
10.4.1 ISP1761 initialization registers
10.3 Clear buffer
10.4 Differences between the ISP1761 and ISP1582 peripheral controllers
Table 96.
Use clear buffer when data needs to be discarded under the following conditions:
For example, to clear a double buffer data IN endpoint 1, set the following registers in the
firmware as:
For example, to clear a double buffer data OUT endpoint 1, set the following registers in
the firmware as:
This section explains the variations between the ISP1761 and ISP1582 peripheral
controllers in terms of register bits and their associated functions.
Endpoint
identifier
EP6TX
EP7RX
EP7TX
1. Assign a value to the Endpoint Index register. It can be any value other than the value
2. Assign DMA Endpoint register = 3h
3. Assign DMA Command register = 0Fh
4. Assign DMA Endpoint register = 3h
5. Assign DMA Command register = 0Fh
1. Assign a value to the DMA Endpoint register. It can be any value other than the value
2. Assign Endpoint Index register = 2h
3. Assign Control Function register = 10Fh
4. Assign Endpoint Index register = 2h
5. Assign Control Function register = 10Fh
•
•
•
IN endpoint: If the host aborts a read operation, the residual data in the IN endpoint
buffer must be cleared using the Clear Buffer command. See
OUT endpoint: If the host aborts a write operation, the residual data in the OUT
endpoint buffer must be cleared using the CLBUF bit. See
assigned to the DMA Endpoint register. In this example, do not assign 3h to the
Endpoint Index register. See remark in
assigned to the Endpoint Index register. In this example, do not assign 2h to the DMA
Endpoint register. See remark in
The ISP1582 supports 16-bit bus access. The register addresses are 2 bytes aligned.
The ISP1761 supports 16-bit and 32-bit bus accesses. To support the 32-bit access,
the DATA_BUS_WIDTH bit in the HW Mode Control register must be initialized.
Endpoint access and programmability
Maximum packet
size
programmable
programmable
programmable
Rev. 05 — 13 March 2008
Double buffering Endpoint type
yes
yes
yes
Section
Section
10.6.1.
…continued
10.6.1.
programmable
programmable
programmable
Hi-Speed USB OTG controller
Table
Table
113.
© NXP B.V. 2008. All rights reserved.
126.
Direction
IN
OUT
IN
ISP1761
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