ISP1761BE STEricsson, ISP1761BE Datasheet - Page 23

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
ISP1761_5
Product data sheet
7.4 Interrupts
It is also possible that the system’s DMA will perform a memory-to-memory type of
transfer between the system memory and the ISP1761 memory. The ISP1761 will be
accessed in PIO mode. Consequently, memory read operations must be preceded by
initializing the Memory register (address 033Ch), as described in
will be generated by the ISP1761 on completing the DMA transfer but an internal
processor interrupt may be generated to signal that the DMA transfer is completed. This is
mainly useful in implementing the double-buffering scheme for data transfer to optimize
the USB bandwidth.
The ISP1761 DMA programming involves:
After programming the preceding parameters, the system’s DMA may be enabled, waiting
for the DREQ to start the transfer or immediate transfer may be started.
The programming of the system’s DMA must match the programming of the ISP1761
DMA parameters. Only one DMA transfer may take place at a time. A PIO mode data
transfer may occur simultaneously with a DMA data transfer, in the same or a different
memory area.
The ISP1761 will assert the IRQ according to the source or event in the HcInterrupt
register. The main steps to enable the IRQ assertion are:
1. Set GLOBAL_INTR_EN (bit 0) in the HW Mode Control register.
2. Define the IRQ active as level or edge in INTR_LEVEL (bit 1) of the HW Mode Control
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Set the active levels of signals DREQ and DACK in the HW Mode Control register.
The DMA Start Address register contains the first memory address at which the data
transfer will start. It must be word-aligned in 16-bit data bus mode and double word
aligned in 32-bit data bus mode.
The programming of the HcDMAConfiguration register specifies:
– The type of transfer that will be performed: read or write.
– The burst size, expressed in bytes, is specified, regardless of the data bus width.
– The transfer length, expressed in number of bytes, defines the number of bursts.
– Enable ENABLE_DMA (bit 1) of the HcDMAConfiguration register to determine the
register.
For the same burst size, a double number of cycles will be generated in 16-bit
mode data bus width as compared to 32-bit mode.
The DREQ will be de-asserted and asserted to generate the next burst, as long as
there are bytes to be transferred. At the end of a transfer, the DREQ will be
de-asserted and an IRQ can be generated if DMAEOTINT (bit 3 in the HcInterrupt
register) is set. The maximum DMA transfer size is equal to the maximum memory
size. The transfer size can be an odd or even number of bytes, as required. If the
transfer size is an odd number of bytes, the number of bytes transferred by the
system’s DMA is equal to the next multiple of two for the 16-bit data bus width or
four for the 32-bit data bus width. For a write operation, however, only the specified
odd number of bytes in the ISP1761 memory will be affected.
assertion of DREQ immediately after setting the bit.
Rev. 05 — 13 March 2008
Hi-Speed USB OTG controller
Section
© NXP B.V. 2008. All rights reserved.
ISP1761
7.3.1. No IRQ
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