ISP1761BE STEricsson, ISP1761BE Datasheet - Page 128

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 150. Interrupt Pulse Width register (address 0280h) bit description
Table 151. Test Mode register (address 0284h) bit allocation
[1]
ISP1761_5
Product data sheet
Bit
15 to 0
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
Symbol
INTR_PULSE_
WIDTH[15:0]
10.8.7 Test Mode register
unchanged
FORCEHS
R/W
7
0
This 1 byte register allows the firmware to set the DP and DM pins to predetermined
states for testing purposes. The bit allocation is given in
Remark: Only one bit can be set to logic 1 at a time.
Table 152. Test Mode register (address 0284h) bit description
[1]
[2]
Bit
7
6 to 5 -
4
3
2
1
0
Either FORCEHS or FORCEFS must be set at a time.
Of the four bits, PRBS, KSTATE, JSTATE and SE0_NAK, only one bit must be set at a time.
Access
R/W
Symbol
FORCEHS
FORCEFS
PRBS
KSTATE
JSTATE
SE0_NAK
R/W
6
0
0
reserved
Value
001Eh Interrupt Pulse Width: The interrupt signal pulse width is configurable
[1]
Description
Force High-Speed: Logic 1
and disables the chirp detection logic.
reserved.
Force Full-Speed: Logic 1
only and disables the chirp detection logic.
Logic 1
K State: Writing logic 1
J State: Writing logic 1
SE0 NAK: Writing logic 1
state. The device only responds to a valid high-speed IN token with a NAK.
R/W
Description
while it is in pulse signaling mode. The minimum pulse width is 3.33 ns
when this register is set to logic 1. The power-on reset value of 1Eh allows
a pulse of 1 s to be generated.
5
0
0
Rev. 05 — 13 March 2008
[2]
sets pins DP and DM to toggle in a predetermined random pattern.
unchanged
FORCEFS
R/W
4
0
[2]
[2]
[2]
sets the DP and DM pins to the J state.
sets the DP and DM pins to the K state.
PRBS
[1]
R/W
[1]
sets pins DP and DM to a high-speed quiescent
3
0
0
forces the physical layer to full-speed mode
forces the hardware to high-speed mode only
KSTATE
Table
R/W
Hi-Speed USB OTG controller
2
0
0
151.
JSTATE
R/W
1
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
SE0_NAK
127 of 163
R/W
0
0
0