ISP1761BE STEricsson, ISP1761BE Datasheet - Page 159

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 103.Interrupt Configuration register (address 0210h)
Table 104.Debug mode settings . . . . . . . . . . . . . . . . . . .107
Table 105.Debug register (address 0212h) bit
Table 106.Debug register (address 0212h) bit
Table 107.DcInterruptEnable - Device Controller Interrupt
Table 108.DcInterruptEnable - Device Controller Interrupt
Table 109.Endpoint Index register (address 022Ch) bit
Table 110.Endpoint Index register (address 022Ch) bit
Table 111.Addressing of endpoint buffers . . . . . . . . . . .110
Table 112.Control Function register (address 0228h) bit
Table 113.Control Function register (address 0228h) bit
Table 114.Data Port register (address 0220h) bit
Table 115.Data Port register (address 0220h) bit
Table 116.Buffer Length register (address 021Ch) bit
Table 117.DcBufferStatus - Device Controller Buffer Status
Table 118.DcBufferStatus - Device Controller Buffer Status
Table 119.Endpoint MaxPacketSize register (address
Table 120.Endpoint MaxPacketSize register (address
Table 121.Endpoint Type register (address 0208h) bit
Table 122.Endpoint Type register (address 0208h) bit
Table 123.Control bits for GDMA read or write (opcode =
Table 124.DMA Command register (address 0230h) bit
Table 125.DMA Command register (address 0230h) bit
Table 126.DMA commands . . . . . . . . . . . . . . . . . . . . . .117
Table 127.DMA Transfer Counter register (address 0234h)
Table 128.DMA Transfer Counter register (address 0234h)
ISP1761_5
Product data sheet
bit description . . . . . . . . . . . . . . . . . . . . . . . .107
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Enable register (address 0214h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Enable register (address 0214h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .109
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
description . . . . . . . . . . . . . . . . . . . . . . . . . . .110
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
description . . . . . . . . . . . . . . . . . . . . . . . . . . .111
description . . . . . . . . . . . . . . . . . . . . . . . . . . .112
description . . . . . . . . . . . . . . . . . . . . . . . . . . .112
description . . . . . . . . . . . . . . . . . . . . . . . . . . .113
register (address 021Eh) bit allocation . . . . .113
register (address 021Eh) bit description . . . .113
0204h) bit allocation . . . . . . . . . . . . . . . . . . . .114
0204h) bit description . . . . . . . . . . . . . . . . . .114
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
description . . . . . . . . . . . . . . . . . . . . . . . . . . .115
00h/01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
description . . . . . . . . . . . . . . . . . . . . . . . . . . .117
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .118
bit description . . . . . . . . . . . . . . . . . . . . . . . .118
Rev. 05 — 13 March 2008
Table 129.DcDMAConfiguration - Device Controller Direct
Table 130.DcDMAConfiguration - Device Controller Direct
Table 131.DMA Hardware register (address 023Ch) bit
Table 132.DMA Hardware register (address 023Ch) bit
Table 133.DMA Interrupt Reason register (address 0250h)
Table 134.DMA Interrupt Reason register (address 0250h)
Table 135.Internal EOT-functional relation with the
Table 136.DMA Interrupt Enable register (address 0254h) bit
Table 137.DMA Endpoint register (address 0258h) bit
Table 138.DMA Endpoint register (address 0258h) bit
Table 139.DMA Burst Counter register (address 0264h) bit
Table 140.DMA Burst Counter register (address 0264h) bit
Table 141.DcInterrupt - Device Controller Interrupt register
Table 142.DcInterrupt - Device Controller Interrupt register
Table 143.DcChipID - Device Controller Chip Identifier
Table 144.Frame Number register (address 0274h) bit
Table 145.Frame Number register (address 0274h) bit
Table 146.DcScratch - Device Controller Scratch register
Table 147.DcScratch - Device Controller Scratch register
Table 148.Unlock Device register (address 027Ch) bit
Table 149.Unlock Device register (address 027Ch) bit
Table 150.Interrupt Pulse Width register (address 0280h) bit
Table 151.Test Mode register (address 0284h) bit
Table 152.Test Mode register (address 0284h) bit
Memory Access Configuration register (address
0238h) bit allocation . . . . . . . . . . . . . . . . . . . 118
Memory Access Configuration register (address
0238h) bit description . . . . . . . . . . . . . . . . . . 119
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 120
bit description . . . . . . . . . . . . . . . . . . . . . . . . 120
DMA_XFER_OK bit . . . . . . . . . . . . . . . . . . . . 121
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
(address 0218h) bit allocation . . . . . . . . . . . . 123
(address 0218h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
register (address 0270h) bit description . . . . 125
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
(address 0278h) bit allocation . . . . . . . . . . . . 126
(address 0278h) bit description . . . . . . . . . . . 126
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Hi-Speed USB OTG controller
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ISP1761
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