ISP1761BE STEricsson, ISP1761BE Datasheet - Page 45

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
[1]
ISP1761_5
Product data sheet
The reserved bits should always be written with the reset value.
Table 35.
Bit
31
30 to 16 -
15
14 to 12 -
11
10
9
8
7
6
5
4 to 3
Symbol
ALL_ATX_RESET
ANA_DIGI_OC
DEV_DMA
COMN_INT
COMN_DMA
DATA_BUS_WIDTH
-
DACK_POL
DREQ_POL
-
HW Mode Control - Hardware Mode Control register (address 0300h) bit
description
Rev. 05 — 13 March 2008
Description
All ATX Reset: For debugging purposes (not used normally).
1 — Enable reset, then write back logic 0
0 — No reset
reserved; write logic 0
Analog Digital Overcurrent: This bit selects analog or digital
overcurrent detection on pins OC1_N/V
0 — Digital overcurrent
1 — Analog overcurrent
reserved; write logic 0
Device DMA: When this bit and bit 9 are set, DC_DREQ and
DC_DACK peripheral signals are selected on the HC_DREQ and
HC_DACK pins.
Common IRQ: When this bit is set, DC_IRQ will be generated on
the HC_IRQ pin.
Common DMA: When this bit and bit 11 are set, the DC_DREQ
and DC_DACK peripheral signals are routed to the HC_DREQ
and HC_DACK pins.
Data Bus Width:
0 — Defines a 16-bit data bus width
1 — Sets a 32-bit data bus width
Remark: Setting this bit will affect all the controllers on the chip:
host controller, peripheral controller and OTG controller.
reserved; write logic 0
DACK Polarity:
1 — Indicates that the DACK input is active HIGH
0 — Indicates active LOW
DREQ Polarity:
1 — Indicates that the DREQ output is active HIGH
0 — Indicates active LOW
reserved; write logic 0
Hi-Speed USB OTG controller
BUS
, OC2_N and OC3_N.
© NXP B.V. 2008. All rights reserved.
ISP1761
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