ISP1761BE STEricsson, ISP1761BE Datasheet - Page 92

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
ISP1761_5
Product data sheet
9.5 OTG controller registers
When an interrupt is generated on HC_IRQ, perform these steps in the interrupt service
routine to get the related OTG status:
The OTG state machine routines are called when any of the inputs is changed. These
inputs come from either OTG registers (hardware) or application program (software). The
outputs of the state machine include control signals to the OTG register (for hardware)
and states or error codes (for software).
The ISP1761 can be configured in OTG mode or in pure host or peripheral mode.
Programming the ISP1761 in OTG mode is done by configuring bit 10 of the OTG control
register. This will enable OTG-specific mechanisms controlled by the OTG control register
bits.
When the OTG protocol is not implemented by the software, the ISP1761 can be used as
a host or a peripheral. In this case, bit 10 of the OTG control register will be set to logic 0.
The host or peripheral functionality is determined by bit 7 of the OTG Control register.
Programming of OTG registers is done by a SET and RESET scheme. An OTG register
has two parts: a 16-bit SET and a 16-bit RESET. Writing logic 1 in a certain position to the
SET-type dedicated 16-bit register part will set the respective bit to logic 1 while writing
logic 1 to the RESET-type 16-bit dedicated register will change the corresponding bit to
logic 0.
Table 79.
Table 80.
Address
037Xh to 038Xh OTG registers
Address
Device ID registers
0370h
OTG Control register
0374h
OTG Interrupt registers
0378h
037Ch
0380h
0384h
2. Set the corresponding bits of the OTG Interrupt Enable Rise and OTG Interrupt
3. Set bit OTG_IRQ_E of the HcInterruptEnable register (bit 10).
4. Set bit GLOBAL_INTR_EN of the HW Mode Control register (bit 0).
1. Read the HcInterrupt register. If OTG_IRQ (bit 10) is set, then step 2.
2. Read the OTG Interrupt Latch register. If any of the bits 0 to 4 are set, then step 3.
3. Read the OTG Status register.
Enable Fall registers.
OTG controller-specific register overview
Address mapping of registers: 32-bit data bus mode
Register
Byte 3
Product ID (read only)
OTG Control (clear)
reserved
OTG Interrupt Latch (clear)
OTG Interrupt Enable Fall (clear)
OTG Interrupt Enable Rise (clear)
Rev. 05 — 13 March 2008
Byte 2
Reset value
-
Byte 1
Vendor ID (read only)
OTG Control (set)
OTG Status (read only)
OTG Interrupt Latch (set)
OTG Interrupt Enable Fall (set)
OTG Interrupt Enable Rise (set)
Hi-Speed USB OTG controller
References
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© NXP B.V. 2008. All rights reserved.
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