ISP1761BE STEricsson, ISP1761BE Datasheet - Page 75

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 71.
ISP1761_5
Product data sheet
Bit
DW7
63 to 32
DW6
31 to 0
DW5
63 to 32
DW4
31 to 6
5
4 to 0
DW3
63
62
61
60
59
58
57
56 to 55
54 to 51
50 to 47
Start and complete split for bulk: bit description
Symbol
reserved
reserved
reserved
reserved
J
NextPTDPointer[4:0] SW — writes
A
H
B
X
SC
reserved
DT
Cerr[1:0]
NakCnt[3:0]
reserved
Access
-
-
-
-
SW — writes
SW — sets
HW — resets
HW — writes
HW — writes
HW — writes
SW — writes
SW — writes 0
HW — updates
-
HW — writes
SW — writes
HW — updates
SW — writes
HW — writes
SW — writes
-
Rev. 05 — 13 March 2008
Value Description
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0 — To increment the PTD pointer.
1 — To enable the next PTD branching.
Next PTD Pointer: Next PTD branching assigned by the PTD
pointer.
Active: Write the same value as that in V.
Halt: This bit corresponds to the Halt bit of the Status field of
TD.
Babble: This bit corresponds to the Babble Detected bit in the
Status field of iTD, siTD or TD.
1 — when babbling is detected, A and V are set to 0.
Transaction Error: This bit corresponds to the Transaction
Error bit in the status field.
0 — Before scheduling
Start/Complete:
0 — Start split
1 — Complete split
-
Data Toggle: Set the Data Toggle bit to start for the PTD.
Error Counter: This field contains the error count for
asynchronous start and complete split (SS/CS) TD. When an
error has no response or bad response, Cerr[1:0] will be
decremented to zero and then Valid will be set to zero. A NAK
or NYET will reset Cerr[1:0]. For details, refer to
Section 4.12.1.2 of
Specification for Universal Serial Bus Rev.
If retry has insufficient time at the beginning of a new SOF, the
first PTD must be this retry. This can be accomplished if
aperiodic PTD is not advanced.
NAK Counter: The V bit is reset if NakCnt decrements to zero
and RL is a non-zero value. Not applicable to isochronous split
transactions.
-
Ref. 2 “Enhanced Host Controller Interface
Hi-Speed USB OTG controller
1.0”.
© NXP B.V. 2008. All rights reserved.
ISP1761
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