ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 102

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Serial peripheral interface (SPI)
17.4.1
102/171
Figure 46. Single master/ single slave application
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode:
In Slave mode:
Figure 47. Generic SS timing diagram
SS internal must be held high continuously.
There are two cases depending on the data/clock timing relationship (see
If CPHA=1 (data latched on 2nd clock edge):
–
If CPHA=0 (data latched on 1st clock edge):
–
MOSI/MISO
(if CPHA=0)
(if CPHA=1)
MSBit
8-BIT SHIFT REGISTER
GENERATOR
Master SS
Slave SS
Slave SS
SS internal must be held low during the entire transmission. This implies that in
single slave applications the SS pin either can be tied to V
standard I/O by managing the SS function by software (SSM= 1 and SSI=0 in the
in the SPICSR register)
SS internal must be held low during byte transmission and pulled high between
each byte to allow the slave to write to the shift register. If SS is not pulled high, a
Write Collision error will occur when the slave writes to the shift register (see
collision error (WCOL) on page
CLOCK
SPI
MASTER
LSBit
Figure
Byte 1
48)
SCK
MOSI
SS
MISO
+5V
106).
Byte 2
MISO
MOSI
SCK
SS
8-BIT SHIFT REGISTER
MSBit
Byte 3
Not used if SS is managed
by software
SLAVE
SS
, or made free for
LSBit
Figure
ST7DALIF2
Write
47):