ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 81

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ST7DALIF2

Manufacturer Part Number
ST7DALIF2
Description
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7DALIF2

8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention
20 years at 55°C.
256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55°C.
Clock Sources
Internal 1% RC oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt
ST7DALIF2
14.6.10
14.6.11
14.6.12
PWMx duty cycle register low (DCRxL)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. It defines the duty cycle of the corresponding PWM
output signal (see
In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of
the PWMx output signal (see
be compared with the 12-bit upcounter value.
Input capture register high (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
Input capture register low (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
Bits 11:0 = ICR[11:0] Input Capture Data.
This is a 12-bit register which is readable by software and cleared by hardware after a reset.
The ATICR register contains captured the value of the 12-bit CNTR register when a rising or
falling edge occurs on the ATIC pin. Capture will only be performed when the ICF flag is
cleared.
DCR7
ICR7
15
7
0
7
DCR6
ICR6
0
Figure
35).
DCR5
ICR5
0
Figure
35). In Output Compare mode, they define the value to
DCR4
ICR4
0
DCR3
ICR11
ICR3
12-bit autoreload timer 2 (AT2)
DCR2
ICR10
ICR2
DCR1
ICR9
ICR1
DCR0
ICR8
ICR0
0
8
0
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