ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 38

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Supply, reset and clock management
9.6
9.6.1
Note:
Caution:
38/171
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three RESET sources as shown in
●
●
●
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic RESET sequence consists of 3 phases as shown in
●
●
●
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay is
automatically selected depending on the clock source chosen by option byte:
Table 11.
The RESET vector fetch phase duration is 2 clock cycles.
When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
If the PLL is enabled by option byte, it outputs the clock after an additional delay of t
(see
Figure 13. RESET sequence phases
Internal RC Oscillator
External clock (connected to CLKIN pin)
External Crystal/Ceramic Oscillator
(connected to OSC1/OSC2 pins)
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 or 4096 CPU clock cycle delay (see table below)
RESET vector fetch
Figure
Section 19.2
11).
Oscillator delay
for further details.
Active Phase
Clock source
256 or 4096 CLOCK CYCLES
INTERNAL RESET
RESET
VECTOR
FETCH
Figure
13:
cycle delay
Figure
CPU clock
4096
256
256
ST7DALIF2
14:
STARTUP