ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 97

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
16.11.3
16.11.4
16.11.5
Bits 7:0 = DCMFA[7:0] Forward Address.
These bits are read by software and set/cleared by hardware.
These 8 bits are used to store the "forward frame" address byte.
DCM forward data register (DCMFD)
Read only
Reset Value: 0000 0000 (00h)
Bits 7:0 = DCMFD[7:0] Forward Data.
These bits are read by software and set/cleared by hardware.
These 8 bits are used to store the "forward frame" data byte.
DCM backward data register (DCMBD)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = DCMBD[7:0] Backward Data.
These bits are set/cleared by software and cleared by hardware after a reset.
These 8 bits are used to store the "backward frame" data byte. The software writes to this
register before enabling the transmit operation.
DCM control register (DCMCR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:4 = Reserved. Forced by hardware to 0.
Bit 3 = DCME DALI Communication Enable.
This bit is set/cleared by software and cleared by hardware after a reset.
When set, it enables DALI communication. It also resets the entire internal finite state
machine.
0: The DCM is not enable to receive/transmit
1: The DCM is enable to receive/transmit
Bit 2 = RTA Receive/Transmit Acknowledge.
This bit is reset by hardware after it has been set by software. It is cleared after a reset.
This bit must be set, after a first DALI frame reception or transmission, to allow the DCM to
perform the next DALI communication.
0: No acknowledge
BD7
FD7
7
7
7
0
BD6
FD6
0
BD5
FD5
0
BD4
FD4
0
DCME
BD3
FD3
DALI communication module
BD2
RTA
FD2
BD1
RTS
FD1
BD0
FTS
FD0
0
0
0
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