ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 104

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Serial peripheral interface (SPI)
Note:
17.4.3
Note:
Note:
17.4.4
Note:
104/171
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
The slave must have the same CPOL and CPHA settings as the master.
2.
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an Overrun condition (see
(OVR) on page
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (See
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge
– Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
– Manage the SS pin as described in
– The SPIF bit is set by hardware
– An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
Write to the SPICSR register to perform the following actions:
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
An access to the SPICSR register while the SPIF bit is set.
A write or a read to the SPIDR register.
(see
must be held low continuously. If CPHA=0 SS must be held low during byte
transmission and pulled up between each byte to let the slave write in the shift
register.
register is cleared.
Figure
Figure
106).
49).
49).
Section 17.4.1
and
Figure
47. If CPHA=1 SS
Overrun condition
ST7DALIF2