ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 45

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
10
Note:
Note:
10.1
10.2
Interrupts
The ST7 core may be interrupted by one of two different methods: maskable hardware
interrupts as listed in the
(TRAP). The Interrupt processing flowchart is shown in
The maskable interrupts must be enabled by clearing the I bit in order to be serviced.
However, disabled interrupts may be latched and processed when they are enabled (see
External interrupt function on page
After reset, all interrupts are disabled.
When an interrupt has to be serviced:
●
●
●
●
The interrupt service routine should finish with the IRET instruction which causes the
contents of the saved registers to be recovered from the stack.
As a consequence of the IRET instruction, the I bit will be cleared and the main program will
resume.
Priority management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware
entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority
defines which one will be serviced first
Interrupts and low power mode
All interrupts allow the processor to leave the Wait low power mode. Only external and
specifically mentioned interrupts allow the processor to leave the Halt low power mode (refer
to the “Exit from Halt“ column in
Non maskable software interrupt
This interrupt is entered when the TRAP instruction is executed regardless of the state of
the I bit. It will be serviced according to the flowchart on
External interrupts
External interrupt vectors can be loaded into the PC register if the corresponding external
interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the
Halt low power mode.
The external interrupt polarity is selected through the
(EICR).
Normal processing is suspended at the end of the current instruction execution.
The PC, X, A and CC registers are saved onto the stack.
The I bit of the CC register is set to prevent additional interrupts.
The PC is then loaded with the interrupt vector of the interrupt to service and the first
instruction of the interrupt service routine is fetched (refer to
mapping
for vector addresses).
Table 15: Interrupt mapping
Table 15: Interrupt
61).
(seeTable 15: Interrupt
mapping).
and a non-maskable software interrupt
External interrupt control register
Figure
Figure
mapping).
19.
19.
Table 15: Interrupt
Interrupts
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