ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 54

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Power saving modes
11.4.1
11.5
Table 21.
54/171
LTCSR1 TB1IE bit
0
0
1
x
Halt mode recommendations
●
●
●
●
●
Active-halt mode
Active-halt mode is the lowest power consumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ instruction. The decision to enter either in
Active-halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the
following table:
Active-Halt control
The MCU can exit Active-halt mode on reception of a specific interrupt (see
Interrupt mapping on page
●
●
When entering Active-halt mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately (see Note 3).
In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
Make sure that an external event is available to wake up the microcontroller from Halt
mode.
When using an external interrupt to wake up the microcontroller, reinitialize the
corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT
instruction. The main reason for this is that the I/O may be wrongly configured due to
external interference or by an unforeseen logical condition.
For the same reason, reinitialize the level sensitiveness of each external interrupt as a
precautionary measure.
The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction
due to a program counter failure, it is advised to clear all occurrences of the data value
0x8E from memory. For example, avoid defining a constant in program memory with
the value 0x8E.
As the HALT instruction clears the interrupt mask in the CC register to allow interrupts,
the user may choose to clear all pending interrupt bits before executing the HALT
instruction. This avoids entering other peripheral interrupt routines after executing the
external interrupt routine corresponding to the wake-up event (reset or external
interrupt).
When exiting Active-halt mode by means of a RESET, a 256 or 4096 CPU cycle delay
occurs. After the start up delay, the CPU resumes operation by fetching the reset vector
which woke it up (see
When exiting Active-halt mode by means of an interrupt, the CPU immediately resumes
operation by servicing the interrupt vector which woke it up (see
ATCSR OVFIE bit
0
1
x
x
Figure
47) or a RESET.
ATCSRCK1 bit
x
x
x
0
26).
ATCSRCK0 bit
0
1
x
x
Active-halt mode disabled
Active-halt mode enabled
Figure
Meaning
Table 15:
26).
ST7DALIF2