ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 39

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
9.6.2
Note:
9.6.3
9.6.4
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Electrical Characteristic
section for more details.
A RESET signal originating from an external source must have a duration of at least
t
therefore the MCU can enter reset state even in Halt mode.
Figure 14. Reset block diagram
Illegal Opcode Reset on page 124
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in the electrical
characteristics section.
External power-on RESET
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until V
the minimum level specified for the selected f
A proper reset signal for a slow rising V
RC network connected to the RESET pin.
Internal low voltage detector (LVD) RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
●
●
The device RESET pin acts as an output that is pulled low when V
V
The LVD filters spikes on V
h(RSTL)in
DD
<V
Power-on RESET
Voltage drop RESET
IT-
RESET
in order to be recognized (see
(falling edge) as shown in
V
DD
R
ON
DD
larger than t
Filter
for more details on illegal opcode reset conditions.
Figure
DD
GENERATOR
Figure
g(VDD)
supply can generally be provided by an external
15.
PULSE
OSC
15). This detection is asynchronous and
to avoid parasitic resets.
frequency.
Supply, reset and clock management
WATCHDOG RESET
ILLEGAL OPCODE RESET
LVD RESET
DD
<V
IT+
INTERNAL
RESET
ON
(rising edge) or
weak pull-up
DD
is over
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