ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 109

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

ST7DALIF2
17.6
Note:
17.7
17.7.1
Note:
Interrupts
Table 47.
The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
Register description
Control register (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault or
Overrun error occurs (SPIF=1, MODF=1 or OVR=1 in the SPICSR register)
Bit 6 = SPE Serial Peripheral Output Enable.
This bit is set and cleared by software. It is also cleared by hardware when, in master mode,
SS=0 (see
SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable.
This bit is set and cleared by software and is cleared by reset. It is used with the SPR[1:0]
bits to set the baud rate. Refer to
0: Divider by 2 enabled
1: Divider by 2 disabled
This bit has no effect in slave mode.
SPI End of Transfer Event
Master Mode Fault Event
Overrun Error
SPIE
7
Interrupt Event
Master mode fault (MODF) on page
Interrupt control bits
SPE
SPR2
Table 48: SPI master mode SCK
MSTR
MODF
Event
SPIF
OVR
Flag
CPOL
105). The SPE bit is cleared by reset, so the
Control
Enable
SPIE
Bit
Serial peripheral interface (SPI)
CPHA
from
Wait
Exit
frequency.
Yes
Yes
Yes
SPR1
from
Exit
Halt
Yes
No
No
SPR0
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0