ST7DALIF2 STMicroelectronics, ST7DALIF2 Datasheet - Page 34

• Manufacturer Part Number: ST7DALIF2
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7DALIF2

• 8 Kbytes Single Voltage Flash Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55°C.
• Clock Sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt

Supply, reset and clock management
9.4
9.4.1
34/171
Figure 11. PLL output frequency timing diagram
When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs
the clock after a delay of t
When the PLL output signal reaches the operating frequency, the LOCKED bit in the
SICSCR register is set. Full PLL accuracy (ACC
t
Refer to
Register description
Main clock control/status register (MCCSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = MCO Main Clock Out enable
This bit is read/write by software and cleared by hardware after a reset. This bit allows to
enable the MCO output clock.
0: MCO clock disabled, I/O port free for general purpose I/O.
1: MCO clock enabled.
Bit 0 = SMS Slow Mode select
This bit is read/write by software and cleared by hardware after a reset. This bit selects the
input clock f
0: Normal mode (f
1: Slow mode (f
STAB
7
0
(see
Section 9.7.4 on page 44
Figure 11
OSC2
CPU =
0
or f
CPU =
4/8 x
input
freq.
OSC2
and
f
OSC2
t
f
STARTUP
OSC2
Section 20.3.3: Internal RC oscillator and PLL on page
STARTUP
/32.
/32)
0
t
.
LOCK
for a description of the LOCKED bit in the SICSR register.
0
LOCKED bit set
PLL
t
STAB
0
) is reached after a stabilization time of
0
t
MCO
ST7DALIF2
131)
SMS
0