HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 113

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

3.5 Subchannel Processing
Data transmission between a FIFO and the connected HFC-channel can be controlled by the subchan-
nel processor. The behavior of this functional unit depends on the selected data flow mode (Channel
Select Mode enabled / disabled) and the operation mode of the HDLC controller (transparent or HDLC
mode). The subchannel controller allows to process less than 8 bits of the transferred FIFO data bytes.
A general overview of the subchannel processor in transmit direction is given in Figure3.11. It shows
an example with three FIFOs connected to one HFC-channel. Details of subchannel processing are
described in the following sections, categorized into the different modes of the data flow and the
HDLC controller.
The essence of the subchannel processor is a bit extraction (transmit) respectively insertion (re-
ceive) unit for every FIFO and a byte mask for every HFC-channel. The subchannel parameters
V_BIT_CNT and V_START_BIT of the register A_SUBCH_CFG define the bits of the HFC-
channel byte that are claimed by the FIFO. On the other side, the channel mask defines the bit values
of those HFC-channel data bits, that are not occupied by FIFO data.
Registers
The FIFO bit extraction / insertion requires two register settings. V_BIT_CNT defines the number
of bits to be extracted / inserted. The start bit can be selected with V_START_BIT in the range of 0
. . . 7. Both values are located in the register A_SUBCH_CFG[FIFO].
The channel mask can be stored in the register A_CH_MSK[FIFO]. This mask is only used for
transmit data. The processed FIFO bits are stored in this register, so it must be re-initialized after
changing the settings in A_SUBCH_CFG[FIFO]. Each HFC-channel has its own mask byte. To
March 2003 (rev. A)
HFC-4S
HFC-8S
Figure 3.11: General structure of the subchannel processor shown with an example of three connected FIFOs
byte m1
byte m1
byte m2
byte m2
byte m3
byte m3
FIFO m
FIFO m
byte n2
byte n2
byte n3
byte n3
byte o2
byte o2
byte o3
byte o3
FIFO n
FIFO n
byte n1
byte n1
FIFO o
FIFO o
byte o1
byte o1
...
...
...
R_FSM_IDX
A_CON_HDLC[7] : V_DATA_FLOW
A_CHANNEL[7] : V_CH_DIR0
A_FIFO_SEQ[7] : V_SEQ_END
FIFO data output
FIFO data output
7
FIFO data output
FIFO data output
7
FIFO data output
FIFO data output
7
: V_IDX
: V_CH_NUM0
0
0
0
Data Sheet
Data flow
7
7
’100’
1
1
20
FIFO
FIFO
data
data
o
o
channel mask
channel mask
FIFO
FIFO
data
data
m
m
(FIFO
(list index 7, FIFO[14,RX])
(receive HFC-channel)
(HFC-channel #20)
(end of chain)
FIFO
FIFO
data
data
m
m
FIFO
FIFO
data
data
m
m
S/T)
FIFO
FIFO
data
data
n
n
FIFO
FIFO
data
data
n
n
0
channel byte
channel byte
Cologne
Chip
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