HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 221

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

11.4 Register description
March 2003 (rev. A)
HFC-4S
HFC-8S
R_BRG_PCM_CFG
Auxiliary bridge and PCM configuration register
0
1
4..2
5
7..6
Bits
0
0
0
0
Value
Reset
V_BRG_EN
V_BRG_MD
(reserved)
V_PCM_CLK
V_ADDR_WRDLY
Name
Auxiliary interface
(write only)
Data Sheet
Description
Auxiliary bridge enable
’0’ = disable (external SRAM can be used)
’1’ = enable (external SRAM is disabled)
Auxiliary bridge data lines mode
Mode of the data bus pins SRD0 SRD7.
’0’ = tristate when no bridge access
’1’ = only tristate when data is read
Must be ’000’.
Clock of the PCM module
’0’ = system clock / 1.5
’1’ = system clock / 3
PCM clock must be 16.384 MHz, system clock is
normaly 24.576 MHz.
Address write delay
Delay from rising edge of pin /SR_WR to address
change for external RAM
’00’ = delay is approximately 3 ns
’01’ = delay is approximately 5 ns
’10’ = delay is approximately 7 ns
’11’ = delay is approximately 9 ns
Cologne
Chip
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