HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 243

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-4S
HFC-8S
R_IRQ_FIFO_BL5
FIFO interrupt register for FIFO block 5
In HDLC mode the end of frame is signaled, while in transparent mode the frequency of
interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If a bit is
’0’, no interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register R_IRQ_OVIEW.
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Value
Reset
V_IRQ_FIFO20_TX
V_IRQ_FIFO20_RX
V_IRQ_FIFO21_TX
V_IRQ_FIFO21_RX
V_IRQ_FIFO22_TX
V_IRQ_FIFO22_RX
V_IRQ_FIFO23_TX
V_IRQ_FIFO23_RX
Name
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Description
Interrupt occured in transmit FIFO 20
Interrupt occured in receive FIFO 20
Interrupt occured in transmit FIFO 21
Interrupt occured in receive FIFO 21
Interrupt occured in transmit FIFO 22
Interrupt occured in receive FIFO 22
Interrupt occured in transmit FIFO 23
Interrupt occured in receive FIFO 23
Cologne
Chip
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