HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 115

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

Each FIFO occupies one or more bits in a HFC-channel data byte. In this example 2 bits are not used
for data. They are filled with the channel mask bits
data bytes which are constructed from three FIFOs.
In the opposite data direction the incoming HFC-channel bytes are stored unchanged in all connected
FIFOs. Therefore it is unnecessary to connect more than one receive FIFO to a receive HFC-channel
if CSM and transparent mode are selected.
3.5.2 HDLC mode
HDLC mode allows to reduce the data rate of a FIFO. In the example of Figure 3.11 FIFO[
delivers 3 bits every 125 s which leads to a FIFO data rate of e.g. 3 kByte/s.
With V_BIT_CNT
during the first 125 s cycle. During the next 125 s cycle the next
March 2003 (rev. A)
HFC-4S
HFC-8S
Table 3.7: Subchannel processing example in CSM combined with transparent mode (transmit direction)
Table 3.6: Subchannel processing example in SM combined with transparent mode (transmit direction)
channel mask:
HFC-channel transmit byte 1:
HFC-channel transmit byte 2:
HFC-channel transmit byte 3:
channel mask:
HFC-channel transmit byte 1:
HFC-channel transmit byte 2:
HFC-channel transmit byte 3:
A_SUBCH_CFG[m,TX] : V_BIT_CNT
A_SUBCH_CFG[n,TX] : V_BIT_CNT
A_SUBCH_CFG[o,TX] : V_BIT_CNT
. . .
. . .
Ü
, the first
Ü
: V_START_BIT
: V_START_BIT
: V_START_BIT
bits of a FIFO byte are transferred to the connected HFC-channel
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Data Sheet
Data flow
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and
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(3 bits)
(beginning at bit 2)
(2 bits)
(beginning at bit 0)
(1 bit)
(bit 6)
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. . .
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. Table 3.7 shows the HFC-channel
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bits of the same byte are
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115 of 273
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