HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 96

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
other. But in practice the connection table is more clear if the same number is chosen for correspond-
ing transmit and receive direction.
A direct connection between two PCM time slots can be set up inside the PCM slot assigner and will
be described in Section 3.3.
The flow controller operates on HFC-channel data. Nevertheless it is programmed with a bitmap of
a FIFO-indexed array register. With this concept it is possible to change the FIFO-to-HFC-channel
assignment of a ready-configured FIFO without re-programming its parameters again.
The internal structure of the flow controller contains
Switching buffers
The switching buffers decouple the data inside the flow controller from the data that is transmit-
ted / received from / to the S/T and PCM interfaces. With every 125 s cycle the switching buffers
change their pointers.
If a byte is read from the FIFO and written into a switching buffer, it is transmitted by the connected
interface during the next 125 s cycle. In the reverse case, a received byte which is stored in a
switching buffer is copied to the FIFO during the next 125 s cycle.
A direct PCM-to-S/T connection delays each data byte two cycles. That means the received byte is
stored in the switching buffer during the first 125 s cycle, then copied into the transmit buffer during
the second 125 s cycle and finally transmitted from the interface during the third 125 s cycle. If
the conference unit is switched on, there is an additional 125 s delay, because the summation of the
whole frame is processed in the memory (see Section 8).
Timed sequence
The data transmission algorithm of the flow controller is FIFO-oriented and handles all FIFOs every
125 s in the following sequence
If a faulty configuration writes data from several sources into the same switching buffer, the last write
access overwrites the previous ones. Only in this case it is necessary to know the process sequence of
the flow controller.
The HFC-4S / 8S has three data flow modes. One of them (FIFO sequence mode) is used to configure
a programmable FIFO sequence which can be used instead of the ascending FIFO numbering. This
is explained in Section 3.4.
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63. FIFO[31,TX]
64. FIFO[31,RX]
2
1. FIFO[0,TX]
2. FIFO[0,RX]
3. FIFO[1,TX]
4. FIFO[1,RX]
. .
.
Due to the FIFO size setup (see Section 4.2) the maximum number of FIFOs might be less than 31.
4 switching buffers, i.e. one for the S/T and PCM interface in transmit and receive direction
each and
3 switches to control the data paths.
2
:
Data Sheet
Data flow
March 2003 (rev. A)
Cologne
Chip