HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 218

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
Data write
Data write requires M[1..0] = ’01’ and is always a posted write. An internal write register is written
by the host write access. Then the data is transferred to the auxiliary interface.
Data read
For read operations the auxiliary bridge uses an internal data buffer. The read access can be performed
in three different modes.
Normal read: (M[1..0] = ’01’) In normal read mode a host read access is immediately transferred
Posted read: (M[1..0] = ’10’) Depending on the selected timing for the desired bridge read operation,
Last read: (M[1..0] = ’11’) The last buffered data byte can be read in last read mode. The buffered
It is possible to perfom byte, word or double word accesses. Word or double word are splitted into
two or four consecutive byte accesses. The accesses are all executed on the same address. Thus word
and double word accesses are useful for FIFO style buffered data transfers from or to an external
device.
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Host
to the auxiliary interface. The host read access must be long enough to pass the data from the
auxiliary interface to the host data bus. Big delays may be involved.
the normal read may not meet the timing requirements of the selected host interface. To ensure
timing constraints when using slow devices the posted read mode can be selected. In this mode
the data of the internal buffer is immediately read by the host interface. Afterwards a read on
the auxiliary interface is initiated to fill the buffer again. So the data of the first host read access
should be ignored.
data is transferred to the host interface and no read access is performed by the auxiliary bridge
afterwards.
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
2 address bytes
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
A[11],CS[0]
CS[1]
CS[2]
M[0]
M[1]
Figure 11.2: Host bridge structure in I/O mapped mode
Auxiliary interface
HFC-4S / HFC-8S
Access
mode
Data Sheet
3
12
/BRG_CS[0..7]
CS[0..2]
Demultiplexer
BRG_A[0..11]
BRG_D[0..7]
/BRG_WR
/BRG_RD
0
7
connected pins
8
2
up to
12
8
2
March 2003 (rev. A)
address
data
control
chip select
address
data
control
chip select
address
data
control
chip select
Cologne
Chip
device #0
device #1
device #7
external
external
external