HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 60

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
2.4 PCMCIA interface
The PCMCIA mode is selected by MODE0
consecutive addresses in the I/O map.
The base I/O address must be 8 byte aligned. The lines A3 . . . A15 are don’t care for I/O accesses.
The address with A2
data read / write.
2.4.1 Attribute memory
After a hardware reset the card’s information structure (CIS) is copied from the EEPROM to the
SRAM, starting with the address shown in Table 2.5. The CIS is located on even numbered addresses
from 0 to 0x3FE in the attribute memory space. The CIS occupies 512 byte. To avoid accesses in
this copy phase the signal IREQ# of the HFC-4S / 8S is active. This is interpreted as ‘wait’ by the
PCMCIA host controller after card insertion.
2.4.2 PCMCIA registers
60 of 273
203 . . . 206, 1 . . . 4
Number
31 . . . 39
43 . . . 51
½
8 . . . 17
is used for register selection via CIP. The address with A2
Table 2.12: Overview of the PCMCIA interface pins
197
198
18
21
22
23
24
25
30
40
7
Universal external bus interface
Name
A15 . . . A8
A7 . . . A0
D15 . . . D8
D7 . . . D0
REG#
IOIS16#
IORD#
IOWR#
OE#
WE#
INPACK#
CE2#
CE1#
IREQ#
RESET
Data Sheet
Address byte 1
Address byte 0
Data byte 1
Data byte 0
16 bit access enable
Read access
High byte enable
Low byte enable
Description
PCMCIA Register and Attr. Mem. Select
Read Enable
Write Enable
PCMCIA Output Enable for Attr. Mem. Read
PCMCIA Write Enable for Conf. Reg. Write
Interrupt request
Reset high active
½
and MODE1
½
. The HFC-4S / 8S occupies eight
March 2003 (rev. A)
Cologne
Chip
¼
is used for