HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 175

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

6.1 PCM interface function
The PCM interface has up to 32, 64 or 128 time slots for receive and transmit data depending on the
PCM clock frequency and the selected mode. The functional block diagram is shown in Figure6.1.
The HFC-4S / 8S has two PCM data pins STIO1 and STIO2 which can both be input or output.
PCM output data is transmitted to two output buffers. These can be enabled independently from each
other. PCM input data can either come from one of the two PCM data pins or from the PCM output
channel. This way PCM data can be looped internally.
Table 6.3: PCM interface configuration with bitmaps of the register A _ SL _ CFG (The reference numbers relate
to the numbers given in Figure 6.1)
Reference
March 2003 (rev. A)
HFC-4S
HFC-8S
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Function
Enable memory read for transmit slot
HFC-channel select for transmit slot
STIO1 output buffer enable for transmit slot
STIO2 output buffer enable for transmit slot
Input buffer select for receive slot
HFC-channel select for receive slot
Enable memory write for receive slot
CHANNEL
CHANNEL
Enable Memory
Enable Memory
Transmit Slot
Receive Slot
Read for
Write for
[1]
[7]
Figure 6.1: PCM interface function block diagram
CHANNEL
CHANNEL
Data Channel
Data Channel
Transmit Slot
Receive Slot
Select for
Select for
PCM interface
[2]
[6]
SLOT
SLOT
Data Sheet
(MUX A)
(MUX B)
(MUX C)
PCM data out
PCM
data out
Receive Slot
Input Buffer
Select for
[5]
V_ROUT
V_ROUT
V_ROUT
V_ROUT
V_ROUT
Bitmap
V_CH_NUM1
V_CH_NUM1
V_ROUT
V_ROUT
A
B
C
Buffer Enable for
Buffer Enable for
STIO0 Output
STIO1 Output
Transmit Slot
Transmit Slot
’01’ (Loop PCM internally)
’10’ (Data In from STIO1)
’11’ (Data In from STIO2)
[3]
[4]
0 . . . 31
0 . . . 31
Value
’10’
’11’
’00’
’00’
Cologne
Chip
175 of 273
STIO1
STIO2