HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 148

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HFC-4S

Manufacturer Part Number
HFC-4S
Description
Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
Manufacturer
Cologne Chip AG
Datasheet
HFC-4S
HFC-8S
5.2 Clock synchronization
5.2.1 Clock synchronization in NT mode
148 of 273
S/T interface in NT mode
RX
TX
divider
÷ 24
192 kHz
8 kHz
PCM data
controller
Figure 5.1: S/T clock synchronization shown with one S/T interface in NT mode
receive
A
DPLL
DPLL
send
192 kHz
B
8 kHz
8 resp. 4 S/T interfaces
controller
S/T data
frame
sync
6.144 MHz
8 kHz
6.144 MHz
S/T interface
DPLL
PCM
Data Sheet
divider
select
s y n c
select
divider
or 8192 kHz
or 4096 kHz
MUX
select
auto-
16384 kHz
÷ 4
MUX
8 / 4
with
3
auto
select
select
input
1
sync
divider
÷ 1.5
MUX
8 kHz from
interface in
TE mode
divider
divider
÷ 2048
÷ 1024
÷ 512
÷ 2
output
sync
select
24.576 MHz
March 2003 (rev. A)
Cologne
Chip
PCM Master
PCM interface
8 kHz
SYNC_I
SYNC_O
C2O
C4IO
F0IO

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