HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 116

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
processed, and so on. When 8 FIFO bits are processed, the next FIFO byte is processed. The byte
boundaries are neglected.
Simple Mode
HDLC mode combined with Simple Mode can transmit one FIFO bit stream (e.g. of FIFO[
the connected HFC-channel. The result is given in Table 3.8
Received HFC-channel data are processed similar. FIFO[
stores 3 bits every 125 s cycle. These bits are taken from the connected HFC-channel at position
[4 . . . 2].
Channel Select Mode
In Channel Select Mode several FIFOs can transmit a bit stream to one connected HFC-channel.
Figure 3.11 with three connected FIFOs to HFC-channel[ ,TX] is taken again as an example. HFC-
channel transmit data for this configuration is shown in Table3.9
Received HFC-channel data are processed similary. Assuming that three receive FIFOs are configured
with the same settings as their corresponding transmit FIFOs, then FIFO[
with 3 kByte/s, FIFO[
116 of 273
8
9
HDLC bit stuffing is not shown in this example.
HDLC bit stuffing is not shown in this example.
Table 3.8: Subchannel processing example in SM combined with HDLC mode (transmit direction)
channel mask:
HFC-channel transmit byte 1:
HFC-channel transmit byte 2:
HFC-channel transmit byte 3:
HFC-channel transmit byte 4:
A_SUBCH_CFG[m,RX] : V_BIT_CNT
. . .
Ò
,RX] receives 2 kByte/s and FIFO[
: V_START_BIT
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Data Sheet
Data flow
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,RX] receives 1 kByte/s.
,RX] with the setting
(3 bits)
(beginning at bit 2)
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,RX] receives a bit stream
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March 2003 (rev. A)
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Cologne
Chip
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,TX]) to