HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 76

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
16 bit processors can either write data with byte or word access. Only 8 bit are used for address
decoding. Thus the address on lines AD31 . . . AD8 are ignored.
A word write is shown in Figure 2.16. FIFO write access have 8 bit or 16 bit width alternatively. The
16 bit processor must support byte access because all other register write accesses must have a width
of 8 bit.
/BE2 and /BE3 must always be ’1’. /BE0 and /BE1 control the low byte and high byte of the data
bus D15 . . . D0 (see Table 2.22 on page 77).
Data is written with
data setup time
Address and /BE require a setup time
is
not required.
An 8 bit write access (low byte) is performed in the same way as it is done with 8 bit processors. Thus
see Figure 2.14 for the timing specification.
76 of 273
AD[31:16]
/WR+/CS
AD[15:8]
/BE[3:2]
/BE[1:0]
Ø
A[7:0]
ALE
À
/RD
. If two consecutive write accesses are on the same address, multiple register address write is
Figure 2.16: Word write access from 16 bit processors in mode 4 (Intel, multiplexed)
Ø
t
address
ALE
Ï Ë
byte enable
t
AS
address
of /WR
and a data hold time
t
AH
t
ALEH
·
Universal external bus interface
/CS in mode 4 (Intel, multiplexed). The HFC-4S / 8S requires a
Ø
Ë
which starts with the of ALE. The hold time of these lines
word write access
Data Sheet
Ø
t
t
DWRS
WR
Ï À
permanently high
permanently high
data
data
.
t
DWRH
t
IDLE
word write access
t
t
WR
DWRS
March 2003 (rev. A)
data
data
Cologne
Chip
t
DWRH