HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 87

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-4S
HFC-8S
R_CTRL
Common control register
0
1
2
3
4
5
7..6
Bits
0
0
0
0
0
0
0
Value
Reset
(reserved)
V_FIFO_LPRIO
V_SLOW_RD
V_EXT_RAM
V_CLK_OFF
V_ST_CLK
Name
(reserved)
Universal external bus interface
(write only)
Data Sheet
Description
Must be ’0’.
FIFO access priority for host accesses
’0’ = normal priority
’1’ = low priority
One additional wait cycle for PCI read accesses
’0’ = normal operation
’1’ = additional wait (must be set for 66 MHz PCI
operation)
Use external RAM
The internal SRAM is switched off when external
SRAM is used.
’0’ = internal SRAM is used in lower 32 kByte
address space
’1’ = external SRAM is used
Must be ’0’.
CLK oscillator
’0’ = normal operation
’1’ = CLK oscillator is switched off
This bit is reset at every write access to the
HFC-4S / 8S.
S/T clock selection
’00’ = system clock / 4
’01’ = system clock / 8
’10’ = system clock (normally unused)
’11’ = system clock / 2 (normally unused)
S/T clock must be 6.144 MHz, system clock is
normaly 24.576 MHz.
Cologne
Chip
87 of 273
0x01