HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 216

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
The HFC-4S / 8S has an auxiliary interface which is designed for connecting up to 8 external devices
with the universal bus interface. This bridge functionality supports 8 bit data bus and up to 12 address
lines. The auxiliary-to-host bridge is typically used to realize a PCI bridge or a PCMCIA bridge
for external devices. The auxiliary interface is implemented parallel to the optional external SRAM
interface, so it can only be used if no external SRAM is connected to the HFC-4S / 8S.
11.1 Interface pins
The auxiliary bridge must be switched on with V_BRG_EN
ble 11.2 shows that the bridge functionality uses some HFC-4S / 8S pins in their second function.
As the first pin functions are associated to the SRAM interface, the external SRAM must be disabled
when the bridge functionality is switched on.
External devices can be accessed by an address bus with up to 12 lines, an 8 bit data bus, up to 8 chip
select signals and two control lines supporting Motorola- or Siemens/Intel-Style interfaces.
216 of 273
G
As the auxiliary interface and the external SRAM use the same chip pins, it is
strongly recommended not to enable the external SRAM and the bridge function-
ality at the same time!
Extract from the register descriptions:
Register
R_CTRL
R_BRG_PCM_CFG
Both register bits are zero by default.
Important !
Pin
54 . . . 61
63 . . . 66
67 . . . 73
74
77 . . . 84
85
87
Table 11.2: HFC-4S / 8S pins of the auxiliary bridge
1st function
SRA0 . . . SRA7
SRA8 . . . SRA11
SRA12 . . . SRA18
NC
SRD0 . . . SRD7
/SR_WR
/SR_OE
Bit
V_EXT_RAM
V_BRG_EN
Auxiliary interface
Data Sheet
Description
The internal SRAM is switched off when ex-
ternal SRAM is used.
’0’ = internal SRAM is used in lower 32 kByte
address space
’1’ = external SRAM is used
’0’ = disable (external SRAM can be used)
’1’ = enable (external SRAM is disabled)
BRG_A0 . . . BRG_A7
BRG_A8 . . . BRG_A11
BRG_D0 . . . BRG_D7
2nd function
/BRG_CS0 . . . /BRG_CS6
/BRG_CS7
/BRG_WR
/BRG_RD
½
in the register V_BRG_EN. Ta-
March 2003 (rev. A)
Cologne
Chip