HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 134

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
4.3.5 FIFO full condition in HDLC receive HFC-channels
Because of the ISDN B-channels not having a hardware based flow control there is no possibility to
stop input data if a receive FIFO is full.
Thus there is no FIFO full condition implemented in the HFC-4S / 8S. The HFC-4S / 8S assumes
that the FIFOs are deep enough that the host processor’s hardware and software is able to avoid any
overflow of the receive FIFOs. Overflow conditions are again more than 31 input frames (resp. 15
frames with 32k RAM) or a memory overflow of the FIFO because of excessive data.
Because HDLC procedures only know a window size of 7 frames no more than 7 frames are sent
without software intervention. Due to the great size of the HFC-4S / 8S FIFOs it is easy to poll the
HFC-4S / 8S even in large time intervalls without having to fear a FIFO overflow condition.
To avoid any undetected FIFO overflows the software driver should check
of frames in the FIFO. If
if there was no reading of a frame in between.
After a detected FIFO overflow condition this FIFO must be reset by setting the FIFO reset bit
V_RES_F in the register R_INC_RES_FIFO.
4.3.6 Transparent mode of the HFC-4S / 8S
It is possible to switch off the HDLC operation for each FIFO independently by the bit
V_HDLC_TRP in register A_CON_HDLC. If this bit is set, data from the FIFO is sent directly
to the S/T or PCM bus interface and data from the S/T or PCM bus interface is sent directly to the
FIFO.
Be sure to switch into transparent mode only if
remain unchanged.
If a transmit FIFO changes to FIFO empty condition no CRC is generated and the last data byte
written into the FIFO is repeated until there is new data.
Normally the last byte is undefined because of the
address. To define the last byte, the last write access to the FIFO must be done without
(see register A_FIFO_DATA0_NOINC).
In receive HFC-channels there is no check on flags or correct CRCs and no status byte added.
Unlike in HDLC mode, where byte synchronization is achieved with HDLC flags, the byte boundaries
are not arbitrary. The data is just the same as it comes from or is sent to the S/T or PCM bus interface.
Transmit and receive transparent data can be done in two ways. The usual way is transporting FIFO
data to the S/T interface with the LSB first as usual in HDLC mode. The second way is transmitting
the bytes in reverse bit order as usual for PCM data. So the first bit is the MSB. The bit order can be
reversed by setting bit V_REV of the register R_FIFO when the FIFO is selected.
134 of 273
-counters are always accessable and have valid data for FIFO input and output.
G
For normal data transmission the register A_SUBCH_CFG must be set to
0x00.
A_SUBCH_CFG must be set to 0x07 for B-channels.
Important !
To use 56 kbit/s restricted mode for U.S. ISDN lines the register
½
and
½
¾
FIFO handling and HDLC controller
are the input and output pointers respectively. Because
¾
is less than the number in the last reading, an overflow took place
Data Sheet
½
¾
-counter pointing to a previously unwritten
. Being in transparent mode the -counters
½
March 2003 (rev. A)
¾
, i.e. the number
Cologne
Chip
½
increment
¾
, the