HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 212

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
10.4 Read only register
212 of 273
R_BERT_STA
Bit error rate test status
2..0
4
5
7..6
R_BERT_ECL
BERT error counter, low byte
7..0
Bits
Bits
0
0
0
0
0
Value
Value
Reset
Reset
Name
V_BERT_SYNC_SRC
V_BERT_SYNC
V_BERT_INV_DATA
(reserved)
Name
V_BERT_ECL
(read only)
(read only)
Data Sheet
BERT
Description
Description
Bits 7 . . . 0 of the BERT error counter
S/T interface selection
Reports which S/T interface is used as sync source.
’000’ = S/T interface 0
’001’ = S/T interface 1
’010’ = S/T interface 2
’011’ = S/T interface 3
’100’ = S/T interface 4
’101’ = S/T interface 5
’110’ = S/T interface 6
’111’ = S/T interface 7
BERT synchronization status
’0’ = BERT not synchronized to input data
’1’ = BERT sync to input data
BERT data inversion
’0’ = BERT receives normal data
’1’ = BERT receives inverted data
This register should be read first to ‘lock’ the value
of the R_BERT_ECH register until
R_BERT_ECH has also been read.
Note: The BERT counter is cleared after reading
this register.
March 2003 (rev. A)
Cologne
Chip
0x1A
0x17