HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 162

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

HFC-4S
HFC-8S
162 of 273
A_ST_WR_STA [ST]
S/T state machine register
This register is used to set a new state. The current state can be read from the A_ST_RD_STA
register.
Before writing this array register the S/T interface must be selected by register R_ST_SEL.
3..0
4
6..5
7
Bits
0
0
0
0
Value
Reset
Name
V_ST_SET_STA
V_ST_LD_STA
V_ST_ACT
V_SET_G2_G3
S/T interface
(write only)
Data Sheet
Description
Start activation / deactivation
Binary value of the new state
(NT: Gx, TE: Fx)
V_ST_LD_STA must also be set to load the state.
Load the new state
’1’ = loads the prepared state (V_ST_SET_STA )
and stops the state machine. This bit needs to be set
for a minimum period of 5.21 s and must be
cleared by software.
’0’ = enables the automatic state machine
(V_ST_SET_STA is ignored). After writing an
invalid state, the state machine goes to deactivated
state (G1, F2).
’00’ = no operation
’01’ = no operation
’10’ = start deactivation
’11’ = start activation
These bits are automatically cleared after
activation / deactivation.
Allow G2 to G3 transition
’0’ = no operation
’1’ = allows transition from G2 to G3 in NT mode
This bit is automatically cleared after the transition
and has no function in TE mode.
March 2003 (rev. A)
Cologne
Chip
0x30