HFC-4S Cologne Chip AG, HFC-4S Datasheet - Page 177

• Manufacturer Part Number: HFC-4S
• Description: Isdn HDLC Fifo Controller With 8 (4) Integrated S/t Interfaces
• Manufacturer: Cologne Chip AG

slot 0 starts with the F0IO pulse. In this example – assuming that PCM30 is configured – F1_0
enables the first CODEC on time slot 0 and shape bytes on R_SH0L and R_SH0H with
and the second CODEC on time slot 1 and shape bytes on R_SH1L and R_SH1H with
The shown shape signals have to be programmed in reverse bit order by
6.3.2 CODEC select via time slot number
Alternatively, external CODECs can be enabled by decoding the time slot number. In this case, two
programmable shape signals SHAPE0 and SHAPE1 are put out with every time slot. The current
time slot number is issued on the pins F_Q6 . . . F_Q0.
The shape signals can be programmed. The example in Figure 6.3 shows shape signals that are
programmed in the same way as shown above (see Section 6.3.1).
F_Q6 . . . F_Q0 must be decoded externally to generate CODEC select signals in dependence on the
PCM time slot.
March 2003 (rev. A)
HFC-4S
HFC-8S
R_PCM_MD0 : V_PCM_ADDR
R_SL_SEL0 : V_SL_SEL0
R_PCM_MD0 : V_PCM_ADDR
R_SL_SEL1 : V_SL_SEL1
R_PCM_MD0 : V_PCM_ADDR
R_SH0L
R_PCM_MD0 : V_PCM_ADDR
R_SH0L
R_PCM_MD0 : V_PCM_ADDR
R_SH0L
R_PCM_MD0 : V_PCM_ADDR
R_SH0L
: V_SH_SEL0
: V_SH_SEL1
: V_SH0L
: V_SH0L
: V_SH0L
: V_SH0L
PCM interface
0
0x1F
0
1
0
1
0xC
0xF8
0xD
0x03
0xE
0x1F
0xF
0xF0
Data Sheet
(R_SL_SEL1 register accessible)
(time slot #1)
(shape bytes R_SH1L and R_SH1H)
(R_SL_SEL0 register accessible)
(time slot #0)
(shape bytes R_SH0L and R_SH0H)
(R_SH0L register accessible)
(0xF8 = ’11111000’
(R_SH0H register accessible)
(0x03 = ’00000011’
(R_SH1L register accessible)
(0x1F = ’00011111’
(R_SH1H register accessible)
(0xF0 = ’11110000’
Ö Ú Ö×
Ö Ú Ö×
Ö Ú Ö×
Ö Ú Ö×
’11000000’)
’00011111’)
’11111000’)
’00001111’)
Cologne
Chip
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