dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet
dp83630sqx
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dp83630sqx Summary of contents
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... LXI Standard ■ Video Synchronization ■ Real Time Networking 4.0 System Diagram PHYTER ® registered trademark of National Semiconductor. © 2011 National Semiconductor Corporation DP83630 3.0 Features ■ IEEE 1588 V1 and V2 supported ■ UDP/IPv4, UDP/IPv6, and Layer2 Ethernet packets supported ■ IEEE 1588 clock synchronization ■ ...
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General Description ......................................................................................................................... 1 2.0 Applications .................................................................................................................................... 1 3.0 Features ........................................................................................................................................ 1 4.0 System Diagram .............................................................................................................................. 1 5.0 Block Diagram ................................................................................................................................ 6 6.0 Key IEEE 1588 Features .................................................................................................................. 6 6.1 IEEE 1588 SYNCHRONIZED CLOCK ......................................................................................... 7 6.1.1 IEEE 1588 ...
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Link Quality Monitor Control and Status ............................................................... 23 9.11.2.2 Checking Current Parameter Values .................................................................... 23 9.11.2.3 Threshold Control ............................................................................................. 23 9.11.3 TDR Cable Diagnostics ............................................................................................... 24 9.11.4 TDR Pulse Generator .................................................................................................. 24 9.11.5 TDR Pulse Monitor ..................................................................................................... 24 9.11.6 ...
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TPI NETWORK CIRCUIT ...................................................................................................... 36 13.2 FIBER NETWORK CIRCUIT .................................................................................................. 37 13.3 ESD PROTECTION .............................................................................................................. 37 13.4 CLOCK IN (X1) RECOMMENDATIONS .................................................................................. 37 14.0 Register Block ............................................................................................................................. 39 14.1 REGISTER DEFINITION ....................................................................................................... 45 14.1.1 Basic Mode Control Register (BMCR) ...
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PTP Receive Configuration Register 2 (PTP_RXCFG2), Page 5 ....................................... 95 14.6.9 PTP Receive Configuration Register 3 (PTP_RXCFG3), Page 5 ....................................... 96 14.6.10 PTP Receive Configuration Register 4 (PTP_RXCFG4), Page 5 ..................................... 97 14.6.11 PTP Temporary Rate Duration Low Register ...
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Block Diagram 6.0 Key IEEE 1588 Features IEEE 1588 provides a time synchronization protocol, often referred to as the Precision Time Protocol (PTP), which syn- chronizes time across an Ethernet network. DP83630 sup- ports IEEE 1588 Real Time Ethernet ...
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FIGURE 1. DP83630 Example System Application 6.1 IEEE 1588 SYNCHRONIZED CLOCK The DP83630 provides several mechanisms for updating the IEEE 1588 clock based on the synchronization protocol re- quired. These methods are listed below. • Directly Read/Writable • Adjustable by ...
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IEEE 1588 Clock Input The IEEE 1588 PTP logic operates on a nominal 125 MHz reference clock generated by an internal Phase Generation Module (PGM). However, options are available to use a di- vided-down version of the PGM clock ...
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Pin Layout Top View Order Number DP83630SQ NS Package Number SQA48A 9 30136259 www.national.com ...
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Pin Descriptions The DP83630 pins are classified into the following interface categories (each interface is described in the sections that follow): • Serial Management Interface • MAC Data Interface • Clock Interface • LED Interface • GPIO Interface • ...
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Signal Name Pin Name RX_DV RX_DV RX_ER RX_ER RXD_0 RXD_0 RXD_1 RXD_1 RXD_2 RXD_2 RXD_3 RXD_3 CRS/CRS_DV CRS/CRS_DV COL COL Type Pin # MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on ...
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CLOCK INTERFACE Signal Name Pin Name CLK_OUT CLK_OUT www.national.com Type Pin # I 34 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83630 and must be connected MHz ...
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LED INTERFACE The DP83630 supports three configurable LED pins. The LEDs support two operational modes which are selected by Signal Name Pin Name LED_LINK LED_LINK LED_SPEED LED_SPEED/ FX_SD LED_ACT LED_ACT 8.5 IEEE 1588 EVENT/TRIGGER/CLOCK INTERFACE Signal Name Pin Name ...
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RESET AND POWER DOWN Signal Name Pin Name RESET_N RESET_N PWRDOWN/INTN PWRDOWN/INTN www.national.com Type Pin # RESET: Active Low input that initializes or re-initializes the DP83630. Asserting this pin low for at least 1 µs will ...
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STRAP OPTIONS The DP83630 uses many of the functional pins as strap op- tions to place the device into specific modes of operation. The values of these pins are sampled at power up or hard reset. During software resets, ...
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Signal Name Pin Name CLK_OUT_EN GPIO1 FX_EN_Z RX_ER LED_CFG CRS/CRS_DV MII_MODE RX_DV PCF_EN GPIO2 RMII_MAS TXD_3 8.9 10 Mb/s AND 100 Mb/s PMD INTERFACE Signal Name Pin Name TD- TD- TD+ TD+ RD- RD- RD+ RD+ FX_SD LED_SPEED/ FX_SD www.national.com ...
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POWER SUPPLY PINS Signal Name Pin Name ANAVSS ANAVSS ANA33VDD ANA33VDD CD_VSS CD_VSS IO_CORE_VSS IO_CORE_VSS IO_VDD IO_VDD IO_VSS IO_VSS VREF VREF DAP DAP 8.11 PACKAGE PIN ASSIGNMENTS SQA48A Pin # Pin Name 1 TX_CLK 2 TX_EN 3 TXD_0 4 ...
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Configuration This section includes information on the various configuration options available with the DP83630. The configuration op- tions described below include: — Media Configuration — Auto-Negotiation — PHY Address and LEDs — Half Duplex vs. Full Duplex — Isolate ...
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The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status. The ANER provides sta- tus on: • Whether or not a Parallel Detect Fault has occurred • Whether or not the Link Partner supports the Next Page function • Whether or ...
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Reset summary in Reset Operation. Since the PHYAD[0] pin has weak internal pull-up resistor and PHYAD[4:1] pins have weak internal pull-down resistors, the default setting for the PHY address is 00001 (01h). Refer to Figure ...
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Link Loss Timer as specified in the IEEE 802.3 specification. In 100BASE-TX mode, an optional fast link loss detection may be enabled by setting the SD_TIME control in the SD_CNFG register. Enabling fast link loss detection will result in the ...
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Auto-Negotiation is not supported in 100BASE-FX operation. Selection of Half or Full-duplex operation is controlled by bit 8 of the Basic Mode Control Register (BMCR), address 00h. If 100BASE-FX mode is strapped using the RX_ER pin, the AN0 strap value ...
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Mb Frequen- cy Offset Indication (FREQ100), address 15h, of the Link Diagnostics Registers - Page 2. Two different versions of the Frequency Offset may be mon- itored through bits [7:0] of register ...
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TDR Cable Diagnostics The DP83630 implements a Time Domain Reflectometry (TDR) method of cable length measurement and evaluation which can be used to evaluate a connected twisted pair cable. The TDR implementation involves sending a pulse out on ei- ...
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The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit defaults to 0 (BIST fail) and will transition on a successful comparison error (mis-compare) occurs, the status bit ...
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Since the reference clock operates at 10 times the data rate for 10 Mb/s operation, transmit data is sampled every 10 clocks. Likewise, receive data will be generated every 10th clock so that an attached device can sample the data ...
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MDIO interface, the station management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83630 with a sequence that can be used to establish synchronization. This preamble may be generated either ...
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Ap- plication software may build a packet, called a PHY Control Frame (PCF passed to the PHY through the MAC Transmit Data interface. The PHY will intercept these packets ...
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FIGURE 6. 100BASE-TX Transmit Block Diagram 29 30136206 www.national.com ...
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Name DATA CODES IDLE AND CONTROL CODES INVALID CODES ...
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The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit polynomial. The output of the closed loop LFSR is X-ORd with the serial NRZ data from the code-group encoder. The result is a scrambled ...
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Base Line Wander Compensation The DP83630 is completely ANSI TP-PMD compliant and in- cludes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TP-PMD defined “killer” pattern. 11.2.2.2 Digital Adaptive Equalization and Gain Control The ...
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MLT-3 to Binary Decoder The DP83630 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data. 11.2.5 Clock Recovery Module The Clock Recovery function is implemented as a Phase de- tector and Loop Filter which ...
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Far-End Fault Since 100BASE-FX does not support Auto-Negotiation, a Far-End Fault facility is included which allows for detection of link failures. When no signal is being received as determined by the Signal Detect function, the device sends a Far-End ...
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The COL signal remains set for the duration of the collision. If the ENDEC is receiving when a collision is detected it is reported immediately (through the COL pin). When heartbeat is enabled, approximately 1 µs after the transmission of ...
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Register space will remain available following a soft reset. 12.4 PTP RESET The entire PTP function, including the IEEE 1588 clock, as- sociated logic, and PTP register space (with two exceptions), can be reset via the PTP_RESET bit in ...
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FIBER NETWORK CIRCUIT Figure 10 shows the recommended circuit for a 100 Mb/s fiber pair interface. 13.3 ESD PROTECTION Typically, ESD precautions are predominantly in effect when handling the devices or board before being installed in a sys- tem. ...
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If a crystal is specified for a lower drive level, a current limiting resistor should be placed in series be- tween X2 and the crystal starting point for evaluating an oscillator circuit, if the ...
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Register Block Offset Access Hex Decimal 00h 0 RW 01h 1 RO 02h 2 RO 03h 3 RO 04h 4 RW 05h 5 RW 06h 6 RW 07h 7 RW 08h-0Fh 8-15 10h 16 RO 11h 17 RW 12h ...
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Offset Access Hex Decimal 14h 20 RW 15h 21 RW 16h 22 RW 17h 23 RW 18h 24 RW 19h 25 RW 1Ah 26 RO 1Bh 27 RO 1Ch 28 RO 1Dh 29 RO 1Eh 30 RO 1Fh 31 RO ...
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REGISTER DEFINITION In the register definitions under the ‘Default’ heading, the following definitions hold true: — Read Write access — Register sets on event occurrence and Self-Clears when event ends — RW/SC = ReadWrite access/Self ...
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Basic Mode Control Register (BMCR) TABLE 14. Basic Mode Control Register (BMCR), address 0x00 Bit Bit Name Default 15 RESET 0, RW/SC 14 LOOPBACK 13 SPEED SELECTION Strap AUTO-NEGOTIATION Strap, RW ENABLE 11 POWER DOWN 10 ISOLATE ...
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Bit Bit Name Default 6 RESERVED UNIDIRECTIONAL 0, RW ENABLE 4:0 RESERVED 0 0000, RO RESERVED: Write ignored, read as 0. Description RESERVED: Write ignored, read as 0. Unidirectional Enable Allow 100 Mb transmit activity ...
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Basic Mode Status Register (BMSR) TABLE 15. Basic Mode Status Register (BMSR), address 0x01 Bit Bit Name Default 15 100BASE-T4 0, RO/P 14 100BASE-TX 1, RO/P FULL DUPLEX 13 100BASE-TX 1, RO/P HALF DUPLEX 12 10BASE-T 1, RO/P FULL ...
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PHY Identifier Register #1 (PHYIDR1) TABLE 16. PHY Identifier Register #1 (PHYIDR1), address 0x02 Bit Bit Name Default 15:0 OUI_MSB 0010 0000 0000 0000, RO/P 14.1.4 PHY Identifier Register #2 (PHYIDR2) TABLE 17. PHY Identifier Register #2 (PHYIDR2), address ...
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Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic ...
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Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. TABLE 19. Auto-Negotiation Link Partner Ability ...
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Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) TABLE 20. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 Bit Bit Name Default ACK ACK2 0, ...
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Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. TABLE 22. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07 Bit Bit Name Default 15 NP ...
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PHY Status Register (PHYSTS) This register provides a single location within the register set for quick access to commonly accessed information. TABLE 23. PHY Status Register (PHYSTS), address 0x10 Bit Bit Name 15 RESERVED 14 MDIX MODE 13 RECEIVE ...
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Bit Bit Name 5 JABBER DETECT 4 AUTO-NEG COMPLETE 3 LOOPBACK STATUS 2 DUPLEX STATUS 1 SPEED STATUS 0 LINK STATUS Default 0, RO Jabber Detect: This bit only has meaning in 10 Mb/s mode. This bit is a duplicate ...
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MII Interrupt Control Register (MICR) This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Link Quality Monitor, Energy Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Com- plete ...
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MII Interrupt Status and Event Control Register (MISR) This register contains event status and enables for the interrupt function event has occurred since the last read of this register, the corresponding status bit will be set. If ...
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Bit Bit Name 8 RHF_INT 0, RO/COR or PCF_INT 7 LQ_INT_EN 6 ED_INT_EN 5 LINK_INT_EN 4 SPD_INT_EN 3 DUP_INT_EN or PTP_INT_EN 2 ANC_INT_EN 1 FHF_INT_EN or CTR_INT_EN 0 RHF_INT_EN or PCF_INT_EN www.national.com Default Receive Error Counter half-full interrupt: Receive error ...
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Page Select Register (PAGESEL) This register is used to enable access to the Link Diagnostics Registers. TABLE 26. Page Select Register (PAGESEL), address 0x13 Bit Bit Name Default 15:3 RESERVED 0000 0000 0000 0, 2:0 PAGE_SEL 000, RW 14.2 ...
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Mb/s PCS Configuration and Status Register (PCSR) This register contains control and status information for the 100BASE Physical Coding Sublayer. TABLE 29. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 Bit Bit Name Default 15 AUTO_CROSSOV ...
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Bit Bit Name Default 1 SCRAM Strap, RW BYPASS 0 DESCRAM Strap, RW BYPASS Description Scrambler Bypass Enable: This bit is set when the FX_EN strap option is selected. In the FX mode, the scrambler is bypassed Scrambler ...
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RMII and Bypass Register (RBR) This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII, RMII, or Single Clock MII mode for Receive or Transmit. In addition, several additional bits are included to allow datapath ...
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Bit Bit Name Default 2 RX_UNF_STS 0, RO 1:0 ELAST_BUF[1:0] 01, RW 14.2.5 LED Direct Control Register (LEDCR) This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs. In ...
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PHY Control Register (PHYCR) This register provides control for PHY functions such as MDIX, BIST, LED configuration, and PHY address. It also provides Pause Negotiation status. TABLE 32. PHY Control Register (PHYCR), address 0x19 Bit Bit Name Default 15 ...
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Bit Bit Name Default 6 LED_CNFG[ LED_CNFG[0] Strap, RW 4:0 PHYADDR[4:0] Strap, RW Description LED Configuration LED_CNFG[1] LED_CNFG[0] Don't care Mode 1, LEDs are configured as follows: LED_LINK = ON ...
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Status/Control Register (10BTSCR) This register is used for control and status for 10BASE-T device operation. TABLE 33. 10Base-T Status/Control Register (10BTSCR), address 0x1A Bit Bit Name 15 RESERVED 14:12 RESERVED 11:9 SQUELCH 8 LOOPBACK_10_DIS 7 LP_DIS 6 FORCE_LINK_10 ...
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CD Test and BIST Extensions Register (CDCTRL1) This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended control and status for the packet BIST function. TABLE 34. CD Test and BIST Extensions Register (CDCTRL1), ...
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PHY Control Register 2 (PHYCR2) This register provides additional general control. TABLE 35. PHY Control Register 2 (PHYCR2), address 0x1C Bit Bit Name 15:14 RESERVED 13 SYNC_ENET EN 12 CLK_OUT RXCLK 11 BC_WRITE 10 PHYTER_COMP 9 SOFT_RESET 8:2 RESERVED ...
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Energy Detect Control (EDCR) This register provides control and status for the Energy Detect function. TABLE 36. Energy Detect Control (EDCR), address 0x1D Bit Bit Name 15 ED_EN 14 ED_AUTO_UP 13 ED_AUTO_DOWN 12 ED_MAN 11 ED_BURST_DIS 10 ED_PWR_STATE 9 ...
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PHY Control Frames Configuration Register (PCFCR) This register provides configuration for the PHY Control Frame mechanism for register access. TABLE 37. PHY Control Frames Configuration Register (PCFCR), address 0x1F Bit Bit Name 15 PCF_STS_ERR 14 PCF_STS_OK 13:9 RESERVED 8 ...
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TEST REGISTERS - PAGE 1 Page 1 Test Registers are accessible by setting bits [2:0] = 001 of PAGESEL (13h). 14.3.1 Signal Detect Configuration (SD_CNFG), Page 1 This register contains Signal Detect configuration control as well as some test ...
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LINK DIAGNOSTICS REGISTERS - PAGE 2 Page 2 Link Diagnostics Registers are accessible by setting bits [2:0] = 010 of PAGESEL (13h). 14.4.1 100 Mb Length Detect Register (LEN100_DET), Page 2 This register contains linked cable length estimation in ...
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TDR Control Register (TDR_CTRL), Page 2 This register contains control for the Time Domain Reflectometry (TDR) cable diagnostics. The TDR cable diagnostics sends pulses down the cable and captures reflection data to be used to estimate cable length and ...
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TDR Window Register (TDR_WIN), Page 2 This register contains sample window control for the Time Domain Reflectometry (TDR) cable diagnostics. The two values con- tained in this register specify the beginning and end times for the window to monitor ...
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Variance Control Register (VAR_CTRL), Page 2 The Variance Control and Data Registers provide control and status for the Cable Signal Quality Estimation function. The Cable Signal Quality Estimation allows a simple method of determining an approximate Signal-to-Noise Ratio for ...
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Link Quality Monitor Register (LQMR), Page 2 This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism for pro- gramming a set of thresholds for DSP parameters. If the thresholds are ...
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Bit Bit Name Default 2 DAGC_LO_WARN 0, RO/COR 1 C1_HI_WARN 0, RO/COR 0 C1_LO_WARN 0, RO/COR Description DAGC Low Warning: This bit indicates the DAGC Low Threshold was exceeded. This register bit will be cleared on read. C1 High Warning: ...
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Link Quality Data Register (LQDR), Page 2 This register provides read/write control of thresholds for the 100 Mb Link Quality Monitor function. The register also provides a mechanism for reading current adapted parameter values. Threshold values may not be ...
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Link Quality Monitor Register 2 (LQMR2), Page 2 This register contains additional controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are ...
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PTP 1588 BASE REGISTERS - PAGE 4 Page 4 PTP 1588 Base Registers are accessible by setting bits [2:0] = 100 of PAGESEL (13h). 14.5.1 PTP Control Register (PTP_CTL), Page 4 This register provides basic control of the PTP ...
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Bit Bit Name Default 1 PTP_DISABLE 0, RW/SC 0 PTP_RESET 0, RW Description Disable PTP Clock: Setting this bit will disable the PTP Clock. Writing this bit will have no effect. This bit is self-clearing and will ...
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PTP Time Data Register (PTP_TDR), Page 4 This register provides a mechanism for reading and writing the 1588 Time and Trigger Control values. The function of this register is determined by controls in the PTP_CTL register. TABLE 51. PTP ...
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PTP Trigger Status Register (PTP_TSTS), Page 4 This register provides status of the PTP 1588 Triggers. The bits in this register indicate the current status of each of the Trigger modules. The error bits will be set if the ...
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PTP Rate Low Register (PTP_RATEL), Page 4 This register contains the low 16-bits of the PTP Rate control. The PTP Rate Control indicates a positive or negative adjustment to the reference clock period in units of 2 REF_CLK_PERIOD +/- ...
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PTP Rate High Register (PTP_RATEH), Page 4 This register contains the upper bits of the PTP Rate control. In addition, it contains a direction control to indicate whether the device is operating faster or slower than the reference clock ...
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PTP Transmit Timestamp Register (PTP_TXTS), Page 4 This register provides a mechanism for reading the Transmit Timestamp. The fields are read in the following order: • Timestamp_ns [15:0] • Overflow_cnt[1:0], Timestamp_ns[29:16] • Timestamp_sec[15:0] • Timestamp_sec[31:16] The Overflow_cnt value indicates ...
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PTP Event Status Register (PTP_ESTS), Page 4 This register provides Status for the Event Timestamp unit. Reading this register provides status for the next Event Timestamp contained in the Event Data Register. If this register Event ...
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PTP Event Data Register (PTP_EDATA), Page 4 This register provides a mechanism for reading the Event Timestamp and extended event status. If present, the extended event status is read prior to reading the Event Timestamp. Presence of the Extended ...
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Bit Bit Name Default 4 E2_DET 0, RO/SC 3 E1_RISE 0, RO/SC 2 E1_DET 0, RO/SC 1 E0_RISE 0, RO/SC 0 E0_DET 0, RO/SC For timestamp fields, the following definition is used for the PTP Event Data Register: TABLE 62. ...
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PTP 1588 CONFIGURATION REGISTERS - PAGE 5 Page 5 PTP 1588 Configuration Registers are accessible by setting bits [2:0] = 101 of PAGESEL (13h). 14.6.1 PTP Trigger Configuration Register (PTP_TRIG), Page 5 This register provides basic configuration for IEEE ...
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PTP Event Configuration Register (PTP_EVNT), Page 5 This register provides basic configuration for IEEE 1588 Events. To write configuration to an Event Timestamp Unit, set the EVNT_WR bit along with the EVNT_SEL and other control information. To read configuration ...
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PTP Transmit Configuration Register 0 (PTP_TXCFG0), Page 5 This register provides configuration for IEEE 1588 Transmit Timestamp operation. TABLE 65. PTP Transmit Configuration Register 0 (PTP_TXCFG0), address 0x16 Bit Bit Name 15 SYNC_1STEP 14 RESERVED 13 DR_INSERT 12 NTP_TS_EN ...
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PTP Transmit Configuration Register 1 (PTP_TXCFG1), Page 5 This register provides data and mask fields to filter the first byte in a PTP Message. This function will be disabled if all the mask bits are set to 0. TABLE ...
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PTP Receive Configuration Register 0 (PTP_RXCFG0), Page 5, This register provides configuration for IEEE 1588 Receive Timestamp operation. TABLE 68. PTP Receive Configuration Register 0 (PTP_RXCFG0), address 0x19 Bit Bit Name 15 DOMAIN_EN 14 ALT_MAST_DIS 13 USER_IP_SEL 12 USER_IP_EN ...
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PTP Receive Configuration Register 1 (PTP_RXCFG1), Page 5 This register provides data and mask fields to filter the first byte in a PTP Message. This function will be disabled if all the mask bits are set to 0. TABLE ...
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PTP Receive Configuration Register 3 (PTP_RXCFG3), Page 5 This register provides extended configuration for IEEE 1588 Receive Timestamp operation. TABLE 71. PTP Receive Configuration Register 3 (PTP_RXCFG3), address 0x1C Bit Bit Name 15:12 TS_MIN_IFG 1100 ACC_UDP 10 ...
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PTP Receive Configuration Register 4 (PTP_RXCFG4), Page 5 This register provides extended configuration for IEEE 1588 Receive Timestamp operation. TABLE 72. PTP Receive Configuration Register 4 (PTP_RXCFG4), address 0x1D Bit Bit Name Default 15 IPV4_UDP_MOD TS_SEC_EN ...
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PTP Temporary Rate Duration High Register (PTP_TRDH), Page 5 This register contains the high 10 bits of the duration in clock cycles to use the Temporary Rate as programmed in the PTP_RATEH and PTP_RATEL registers. Since the Temporary Rate ...
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PHY Status Frame Configuration Register 1 (PSF_CFG1), Page 6 This register provides configuration for the PHY Status Frame function. Specifically, the 16-bit value in this register is used as the first 16-bits of the PTP Header data for the ...
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PTP SFD Configuration Register (PTP_SFDCFG), Page 6 This register provides configuration to enable outputting the RX and TX Start-of-Frame (SFD) signals on GPIO pins. Note that GPIO assignments are not exclusive. TABLE 80. PTP SFD Configuration Register (PTP_SFDCFG), address ...
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PTP Offset Register (PTP_OFF), Page 6 This register provides the byte offset to the PTP message in a Layer2 Ethernet frame. TABLE 84. PTP Offset Register (PTP_OFF), address 0x1D Bit Bit Name Default 15:8 RESERVED 0000 0000, RO 7:0 ...
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Absolute Maximum Ratings 4) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT ...
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Pin Symbol Parameter Types V PMD Input 10BASE-T Receive Threshold TH Pair I Supply 100BASE-TX (Full Duplex) dd100 I Supply 10BASE-T (Full Duplex) dd10 I Supply Power Down Mode dd Note 5: For I measurements, outputs are not loaded dd ...
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AC SPECIFICATIONS 18.2.1 Power Up Timing Parameter Description T2.1.1 Post Power Up Stabilization time prior to MDC preamble for register accesses T2.1.2 Hardware Configuration Latch-in Time from power up T2.1.3 Hardware Configuration pins transition to output drivers Note: In ...
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Reset Timing Parameter Description T2.2.1 Post RESET Stabilization time prior to MDC preamble for register accesses T2.2.2 Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard) T2.2.3 Hardware Configuration pins transition to output drivers T2.2.4 ...
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MII Serial Management Timing Parameter Description T2.3.1 MDC to MDIO (Output) Delay Time T2.3.2 MDIO (Input) to MDC Setup Time T2.3.3 MDIO (Input) to MDC Hold Time T2.3.4 MDC Frequency 18.2.4 100 Mb/s MII Transmit Timing Parameter Description T2.4.1 ...
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Mb/s MII Receive Timing Parameter Description T2.5.1 RX_CLK High/Low Time T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay Note: RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. ...
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MII Transmit Packet Deassertion Timing Parameter Description T2.7.1 TX_CLK to PMD Output Pair Deassertion 100BASE-TX and 100BASE-FX modes Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the ...
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MII Receive Packet Latency Timing Parameter Description T2.9.1 Carrier Sense ON Delay T2.9.2 Receive Data Latency Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group ...
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Mb/s MII Transmit Timing Parameter Description T2.11.1 TX_CLK High/Low Time T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK falling edge T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rising edge Note: An attached Mac should drive the transmit signals using ...
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MII Transmit Timing (Start of Packet) Parameter Description T2.13.1 Transmit Output Delay from the Falling Edge of TX_CLK Note: 1 bit time = 100 Mb/s. 18.2.14 10BASE-T MII Transmit Timing (End of Packet) Parameter Description ...
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MII Receive Timing (Start of Packet) Parameter Description T2.15.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) T2.15.2 RX_DV Latency T2.15.3 Receive Data Latency Note: 10BASE-T RX_DV Latency is measured from first bit of preamble on ...
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Mb/s Heartbeat Timing Parameter Description T2.17.1 CD Heartbeat Delay T2.17.2 CD Heartbeat Duration 18.2.18 10 Mb/s Jabber Timing Parameter Description T2.18.1 Jabber Activation Time T2.18.2 Jabber Deactivation Time Notes Min All 10 Mb/s modes All 10 Mb/s modes ...
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Normal Link Pulse Timing Parameter Description T2.19.1 Pulse Width T2.19.2 Pulse Period Note: These specifications represent transmit timings. 18.2.20 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameter Description T2.20.1 Clock, Data Pulse Width T2.20.2 Clock Pulse to Clock Pulse ...
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Signal Detect Timing Parameter Description T2.21.1 SD Internal Turn-on Time T2.21.2 SD Internal Turn-off Time Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant. Note: Fast Link-loss detect is enabled by setting the SD_CNFG[8] register ...
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Mb/s Internal Loopback Timing Parameter Description T2.23.1 TX_EN to RX_DV Loopback Note: Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN. 18.2.24 RMII Transmit Timing (Slave Mode) Parameter Description T2.24.1 X1 Clock Period ...
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RMII Transmit Timing (Master Mode) Parameter Description T2.25.1 RX_CLK, TX_CLK, CLK_OUT Period T2.25.2 TXD[1:0], TX_EN Data Setup to RX_CLK, TX_CLK, CLK_OUT rising edge T2.25.3 TXD[1:0], TX_EN Data Hold from RX_CLK, TX_CLK, CLK_OUT rising edge T2.25.4 RX_CLK, TX_CLK, CLK_OUT to ...
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RMII Receive Timing (Slave Mode) Parameter Description T2.26.1 X1 Clock Period T2.26.2 RXD[1:0], CRS_DV, and RX_ER output delay from X1 rising edge T2.26.3 CRS ON delay T2.26.4 CRS OFF delay T2.26.5 RXD[1:0] and RX_ER latency Note: Per the RMII ...
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RMII Receive Timing (Master Mode) Parameter Description T2.27.1 RX_CLK, TX_CLK, CLK_OUT Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from RX_CLK, TX_CLK, CLK_OUT rising edge T2.27.3 CRS ON delay T2.27.4 CRS OFF delay T2.27.5 RXD[1:0] and RX_ER ...
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RX_CLK Timing (RMII Master Mode) Parameter Description T2.28.1 RX_CLK High Time T2.28.2 RX_CLK Low Time T2.28.3 RX_CLK Period Note: The High Time and Low Time will add ns. 18.2.29 CLK_OUT Timing (RMII Slave Mode) Parameter Description ...
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Single Clock MII (SCMII) Transmit Timing Parameter Description T2.30.1 X1 Clock Period T2.30.2 TXD[3:0], TX_EN Data Setup T2.30.3 TXD[3:0], TX_EN Data Hold T2.30.4 X1 Clock to PMD Output Pair Latency (100 Mb) Note: Latency measurement is made from the ...
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Single Clock MII (SCMII) Receive Timing Parameter Description T2.31.1 X1 Clock Period T2.31.2 RXD[3:0], RX_DV and RX_ER output delay From X1 rising edge T2.31.3 CRS ON delay T2.31.4 CRS OFF delay T2.31.5 RXD[3:0] and RX_ER latency Note: Output delays ...
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Mb TX_CLK Timing Parameter Description T2.32 TX_CLK delay Note TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit MII data. Notes Min 100 ...
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... Physical Dimensions 20.0 Ordering Information Order Number DP83630SQ DP83630SQE DP83630SQX www.national.com inches (millimeters) unless otherwise noted 48-Lead LLP Plastic Quad Package, LLP NS Package Number SQA48A Package Marking DP83630SQ DP83630SQ DP83630SQ 124 Supplied As Reel of 1000 Reel of 250 Reel of 2500 ...
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