dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 75

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

14:4
Bit
2:1
15:0
15
Bit
3
0
14.4.7 Variance Control Register (VAR_CTRL), Page 2
The Variance Control and Data Registers provide control and status for the Cable Signal Quality Estimation function. The Cable
Signal Quality Estimation allows a simple method of determining an approximate Signal-to-Noise Ratio for the 100 Mb receiver.
This register contains the programmable controls and status bits for the variance computation, which can be used to make a simple
Signal-to-Noise Ratio estimation.
14.4.8 Variance Data Register (VAR_DATA), Page 2
This register contains the 32-bit Variance Sum. The contents of the data are valid only when VAR_RDY is asserted in the
VAR_CTRL register. Upon detection of VAR_RDY asserted, software should set the VAR_FREEZE bit in the VAR_CTRL register
to prevent loading of a new value into the VAR_DATA register. Since the Variance Data value is 32-bits, two reads of this register
are required to get the full value.
VAR_FREEZE
VAR_ENABLE
VAR_TIMER
RESERVED
VAR_RDY
VAR_DATA
Bit Name
Bit Name
TABLE 45. Variance Control Register (VAR_CTRL), address 0x1A
000 0000 0000, RO RESERVED: Writes ignored, read as 0.
TABLE 46. Variance Data Register (VAR_DATA), address 0x1B
0000 0000 0000
0000, RO
Default
Default
00, RW
0, RW
0, RW
0, RO
Variance Data:
Two reads are required to return the full 32-bit Variance Sum value. Following
setting the VAR_FREEZE control, the first read of this register will return the low
16 bits of the Variance data. A second read will return the high 16 bits of Variance
data.
Variance Data Ready Status:
Indicates new data is available in the Variance data register. This bit will be
automatically cleared after two consecutive reads of VAR_DATA.
Freeze Variance Registers:
Freeze VAR_DATA register.
This bit is ensures that VAR_DATA register is frozen for software reads. This bit
is automatically cleared after two consecutive reads of VAR_DATA.
Variance Computation Timer (in ms):
Selects the Variance computation timer period. After a new value is written,
computation is automatically restarted. New variance register values are loaded
after the timer elapses.
Var_Timer = 0 => 2 ms timer (default)
Var_Timer = 1 => 4 ms timer
Var_Timer = 2 => 6 ms timer
Var_Timer = 3 => 8 ms timer
Time units are actually 2
Variance Enable:
Enable Variance computation. Off by default.
75
17
cycles of an 8 ns clock, or 1.048576 ms.
Description
Description
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