dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 64

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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Bit
15
14
13
12
11
10
9
8
7
14.2.6 PHY Control Register (PHYCR)
This register provides control for PHY functions such as MDIX, BIST, LED configuration, and PHY address. It also provides Pause
Negotiation status.
BIST_STATUS
BP_STRETCH
FORCE_MDIX
BIST_START
PAUSE_RX
PAUSE_TX
MDIX_EN
Bit Name
BIST_FE
PSR_15
TABLE 32. PHY Control Register (PHYCR), address 0x19
0, RW/SC
0, LL/RO
Default
1, RW
0, RW
0, RW
0, RW
0, RW
0, RO
0, RO
Auto-MDIX Enable:
1 = Enable Auto-neg Auto-MDIX capability.
0 = Disable Auto-neg Auto-MDIX capability.
Force MDIX:
1 = Force MDI pairs to cross.
0 = Normal operation.
Pause Receive Negotiated:
Indicates that pause receive should be enabled in the MAC. Based on ANAR
[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3,
“Pause Resolution”, only if the Auto-Negotiated Highest Common Denominator
is a full duplex technology.
Pause Transmit Negotiated:
Indicates that pause transmit should be enabled in the MAC. Based on ANAR
[11:10] and ANLPAR[11:10] settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3,
Pause Resolution, only if the Auto-Negotiated Highest Common Denominator is
a full duplex technology.
BIST Force Error:
1 = Force BIST Error.
0 = Normal operation.
This bit forces a single error, and is self clearing.
BIST Sequence select:
1 = PSR15 selected.
0 = PSR9 selected.
BIST Test Status:
1 = BIST pass.
0 = BIST fail. Latched, cleared when a BIST failure occurs or BIST is stopped.
For a count number of BIST errors, see the BIST Error Count in the CDCTRL1
register.
BIST Start:
Writes:
1 = BIST start. Writing 1 to this bit enables transmission of BIST packets and
enables the receive BIST engine to start looking for packet traffic.
0 = BIST stop. Stop the BIST. Writing 0 to this bit also clears the BIST_STATUS
bit.
Reads:
1 = BIST active. This bit reads 1 after the transmit BIST engine has been enabled
and the receive BIST engine has detected packet traffic.
0 = BIST inactive. This bit will read 0 if the BIST is disabled or if the BIST is enabled
but no receive traffic has been detected.
Bypass LED Stretching:
This will bypass the LED stretching and the LEDs will reflect the internal value.
1 = Bypass LED stretching.
0 = Normal operation.
(Receive on TD pair, Transmit on RD pair)
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