dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 23

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

offset can be determined using the register 100 Mb Frequen-
cy Offset Indication (FREQ100), address 15h, of the Link
Diagnostics Registers - Page 2.
Two different versions of the Frequency Offset may be mon-
itored through bits [7:0] of register FREQ100 (15h). The first
is the long-term Frequency Offset. The second is the current
Frequency Control value, which includes short-term phase
adjustments and can provide information on the amount of
jitter in the system.
9.11.1.5 Cable Signal Quality Estimation
The cable signal quality estimator keeps a simple tracking of
results of the DSP and can be used to generate an approxi-
mate Signal-to-Noise Ratio for the 100 Mb receiver. This
information is available to software through the Link Diagnos-
tics Registers - Page 2: Variance Control Register
(VAR_CTRL), address 1Ah and Variance Data Register
(VAR_DATA), address 1Bh.
The variance computation times (VAR_TIMER) can be cho-
sen from the set of {2, 4, 6, 8} ms. The 32-bit variance sum
can be read by two consecutive reads of the VAR_DATA reg-
ister. This sum can be used to compute an SNR estimate by
software using the following equation:
SNR = 10log
9.11.2 Link Quality Monitor
The Link Quality Monitor allows a method to generate an
alarm when the DSP adaption strays from a programmable
window. This could occur due to changes in the cable which
could indicate a potential problem. Software can program
thresholds for the following DSP parameters to be used to
interrupt the system:
— Digital Equalizer C1 Coefficient (DEQ C1)
— Digital Adaptive Gain Control (DAGC)
— Digital Base-Line Wander Control (DBLW)
— Recovered Clock Long-Term Frequency Offset (FREQ)
— Recovered Clock Frequency Control (FC)
— Signal-to-Noise Ratio (SNR) Variance
Software is expected to read initial adapted values and then
program the thresholds based on an expected valid range.
This mechanism takes advantage of the fact that the DSP
adaptation should remain in a relatively small range once a
valid link has been established.
9.11.2.1 Link Quality Monitor Control and Status
Control of the Link Quality Monitor is done through the Link
Quality Monitor Register (LQMR), address 1Dh and the Link
Quality Data Register (LQDR), address 1Bh of the Link Diag-
Note that values are signed 2-s complement values except
for DAGC and Variance which are always positive. The max-
imum SNR Variance is calculated by assuming the worst-
case squared error (144) is accumulated every 8 ns for
8*2
20
DEQ_C1
DAGC
DBLW
Frequency Offset
Frequency Control
SNR Variance
ns (roughly 8 ms or exactly 1,048,576 clock cycles).
Parameter
10
((37748736 * VAR_TIMER) / Variance).
Minimum Value
TABLE 4. Link Quality Monitor Parameter Ranges
-128
-128
-128
-128
0
0
Maximum Value
+2304
+127
+255
+127
+127
+127
23
nostics Registers - Page 2. The LQMR register includes a
global enable to enable the Link Quality Monitor function. In
addition, it provides warning status from both high and low
thresholds for each of the monitored parameters except SNR
Variance.. The LQMR2 register provides warning status for
the high threshold of SNR Variance (upper 16 bits); there is
no low threshold. Note that individual low or high parameter
threshold comparisons can be disabled by setting to the min-
imum or maximum values.
To allow the Link Quality Monitor to interrupt the system, the
Interrupt must be enabled through the interrupt control regis-
ters, MICR (11h) and MISR (12h).
The Link Quality Monitor may also be used to automatically
reset the DSP and restart adaption. Separate enable bits in
LQMR and LQMR2 allow for automatic reset based on each
of the parameter values. If enabled, a violation of one of the
thresholds will result in a restart of the DSP adaption. In ad-
dition if the PCSR:SD_OPTION register bit is set to 0, the
violation will also result in a drop in Link Status.
9.11.2.2 Checking Current Parameter Values
Prior to setting Threshold values, it is recommended that soft-
ware check current adapted values. The thresholds may then
be set relative to the adapted values. The current adapted
values can be read using the LQDR register by setting the
SAMPLE_PARAM bit [13] of LQDR, address (1Eh).
For example, to read the DBLW current value:
1.
2.
9.11.2.3 Threshold Control
The LQDR (1Eh) register also provides a method of program-
ming high and low thresholds for each of the five parameters
that can be monitored. The register implements an indirect
read/write mechanism.
Writes are accomplished by writing data, address, and a write
strobe to the register. Reads are accomplished by writing the
address to the register, and reading back the value of the se-
lected threshold. Setting thresholds to the maximum or mini-
mum values will disable the threshold comparison since
values have to exceed the threshold to generate a warning
condition.
Warnings are not generated if the parameter is equal to the
threshold. By default, all thresholds are disabled by setting to
the minimum or maximum values. The
parameters and range of values:
For example, to set the DBLW Low threshold to -38:
1.
2.
Write 2400h to LQDR (1Eh) to set the SAMPLE_PARAM
bit and set the LQ_PARAM_SEL[2:0] to 010.
Read LQDR (1Eh). Current DBLW value is returned in
the low 8 bits.
Write 14DAh to LQDR to set the Write_LQ_Thr bit, select
the DBLW Low Threshold, and write data of -38 (0xDA).
Write 8000 to LQMR to enable the Link Quality Monitor
(if not already enabled).
Min (2-s comp)
0x0000
0x80
0x00
0x80
0x80
0x80
Max (2-s comp)
Table 4
0x900
0x7F
0xFF
0x7F
0x7F
0x7F
shows the five
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