dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 70

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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13:9
Bit
7:6
4:1
15
14
8
5
0
14.2.11 PHY Control Frames Configuration Register (PCFCR)
This register provides configuration for the PHY Control Frame mechanism for register access.
PCF_STS_ERR
PCF_INT_CTL
PCF_STS_OK
PCF_DA_SEL
PCF_BC_DIS
RESERVED
PCF_BUF
Bit Name
PCF_EN
TABLE 37. PHY Control Frames Configuration Register (PCFCR), address 0x1F
0, RO/COR
0, RO/COR
00 000, RO
0 000, RW
Strap, RW
Default
00, RW
0, RW
0, RW
PHY Control Frame Error Detected:
Indicates an error was detected in a PCF Frame since the last read of
this register. This bit will be cleared on read.
PHY Control Frame OK:
Indicates a PCF Frame has completed without error since the last read
of this register. This bit will be cleared on read.
Reserved: Writes ignored, read as 0
Select MAC Destination Address for PHY Control Frames:
0 : Use MAC Address [08 00 17 0B 6B 0F]
1 : Use MAC Address [08 00 17 00 00 00]
The device will also recognize packets with the above address with the
Multicast bit set (i.e. 09 00 17 ...).
PHY Control Frame Interrupt Control:
Setting either of these bits enables control and status of the PCF
Interrupt through the MISR Register (taking the place of the RHF
Interrupt).
00 = PCF Interrupts Disabled
x1 = Interrupt on PCF Frame OK
1x = Interrupt on PCF Frame Error
PHY Control Frame Broadcast Disable:
By default, the device will accept broadcast PHY Control Frames which
have a PHY Address field of 0x1F. If this bit is set to a 1, the PHY Control
Frame must have a PHY Address field that exactly matches the device
PHY Address.
PHY Control Frame Buffer Size:
Determines the buffer size for transmit to allow PHY Control Frame
detection. All packets will be delayed as they pass through this buffer.
If set to 0, packets will not be delayed and PHY Control frames will be
truncated after the Destination Address field.
PHY Control Frame Enable:
Enables Register writes using PHY Control Frames.
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Description