dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 4

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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14.0 Register Block ............................................................................................................................. 39
13.1 TPI NETWORK CIRCUIT ...................................................................................................... 36
13.2 FIBER NETWORK CIRCUIT .................................................................................................. 37
13.3 ESD PROTECTION .............................................................................................................. 37
13.4 CLOCK IN (X1) RECOMMENDATIONS .................................................................................. 37
14.1 REGISTER DEFINITION ....................................................................................................... 45
14.2 EXTENDED REGISTERS - PAGE 0 ....................................................................................... 59
14.3 TEST REGISTERS - PAGE 1 ................................................................................................ 71
14.4 LINK DIAGNOSTICS REGISTERS - PAGE 2 ........................................................................... 72
14.5 PTP 1588 BASE REGISTERS - PAGE 4 ................................................................................. 80
14.6 PTP 1588 CONFIGURATION REGISTERS - PAGE 5 ............................................................... 90
14.1.1 Basic Mode Control Register (BMCR) ............................................................................ 46
14.1.2 Basic Mode Status Register (BMSR) ............................................................................. 48
14.1.3 PHY Identifier Register #1 (PHYIDR1) ........................................................................... 49
14.1.4 PHY Identifier Register #2 (PHYIDR2) ........................................................................... 49
14.1.5 Auto-Negotiation Advertisement Register (ANAR) ........................................................... 50
14.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) ............................. 51
14.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) ............................... 52
14.1.8 Auto-Negotiate Expansion Register (ANER) ................................................................... 52
14.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) ............................................... 53
14.1.10 PHY Status Register (PHYSTS) .................................................................................. 54
14.1.11 MII Interrupt Control Register (MICR) ........................................................................... 56
14.1.12 MII Interrupt Status and Event Control Register (MISR) .................................................. 57
14.1.13 Page Select Register (PAGESEL) ............................................................................... 59
14.2.1 False Carrier Sense Counter Register (FCSCR) ............................................................. 59
14.2.2 Receiver Error Counter Register (RECR) ....................................................................... 59
14.2.3 100 Mb/s PCS Configuration and Status Register (PCSR) ................................................ 60
14.2.4 RMII and Bypass Register (RBR) .................................................................................. 62
14.2.5 LED Direct Control Register (LEDCR) ........................................................................... 63
14.2.6 PHY Control Register (PHYCR) .................................................................................... 64
14.2.7 10Base-T Status/Control Register (10BTSCR) ................................................................ 66
14.2.8 CD Test and BIST Extensions Register (CDCTRL1) ........................................................ 67
14.2.9 PHY Control Register 2 (PHYCR2) ............................................................................... 68
14.2.10 Energy Detect Control (EDCR) ................................................................................... 69
14.2.11 PHY Control Frames Configuration Register (PCFCR) ................................................... 70
14.3.1 Signal Detect Configuration (SD_CNFG), Page 1 ............................................................ 71
14.4.1 100 Mb Length Detect Register (LEN100_DET), Page 2 .................................................. 72
14.4.2 100 Mb Frequency Offset Indication Register (FREQ100), Page 2 ..................................... 72
14.4.3 TDR Control Register (TDR_CTRL), Page 2 ................................................................... 73
14.4.4 TDR Window Register (TDR_WIN), Page 2 .................................................................... 74
14.4.5 TDR Peak Register (TDR_PEAK), Page 2 ..................................................................... 74
14.4.6 TDR Threshold Register (TDR_THR), Page 2 ................................................................. 74
14.4.7 Variance Control Register (VAR_CTRL), Page 2 ............................................................. 75
14.4.8 Variance Data Register (VAR_DATA), Page 2 ................................................................ 75
14.4.9 Link Quality Monitor Register (LQMR), Page 2 ................................................................ 76
14.4.10 Link Quality Data Register (LQDR), Page 2 .................................................................. 78
14.4.11 Link Quality Monitor Register 2 (LQMR2), Page 2 ......................................................... 79
14.5.1 PTP Control Register (PTP_CTL), Page 4 ...................................................................... 80
14.5.2 PTP Time Data Register (PTP_TDR), Page 4 ................................................................. 82
14.5.3 PTP Status Register (PTP_STS), Page 4 ....................................................................... 82
14.5.4 PTP Trigger Status Register (PTP_TSTS), Page 4 .......................................................... 83
14.5.5 PTP Rate Low Register (PTP_RATEL), Page 4 .............................................................. 84
14.5.6 PTP Rate High Register (PTP_RATEH), Page 4 ............................................................. 85
14.5.7 PTP Read Checksum (PTP_RDCKSUM), Page 4 ........................................................... 85
14.5.8 PTP Write Checksum (PTP_WRCKSUM), Page 4 ........................................................... 85
14.5.9 PTP Transmit Timestamp Register (PTP_TXTS), Page 4 ................................................. 86
14.5.10 PTP Receive Timestamp Register (PTP_RXTS), Page 4 ................................................ 86
14.5.11 PTP Event Status Register (PTP_ESTS), Page 4 .......................................................... 87
14.5.12 PTP Event Data Register (PTP_EDATA), Page 4 .......................................................... 88
14.6.1 PTP Trigger Configuration Register (PTP_TRIG), Page 5 ................................................. 90
14.6.2 PTP Event Configuration Register (PTP_EVNT), Page 5 .................................................. 91
14.6.3 PTP Transmit Configuration Register 0 (PTP_TXCFG0), Page 5 ....................................... 92
14.6.4 PTP Transmit Configuration Register 1 (PTP_TXCFG1), Page 5 ....................................... 93
14.6.5 PHY Status Frame Configuration Register 0 (PSF_CFG0), Page 5 .................................... 93
14.6.6 PTP Receive Configuration Register 0 (PTP_RXCFG0), Page 5, ...................................... 94
14.6.7 PTP Receive Configuration Register 1 (PTP_RXCFG1), Page 5 ....................................... 95
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