dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 16

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

www.national.com
CLK_OUT_EN
FX_EN_Z
LED_CFG
MII_MODE
PCF_EN
RMII_MAS
TD-
TD+
RD-
RD+
FX_SD
8.9 10 Mb/s AND 100 Mb/s PMD INTERFACE
Signal Name
Signal Name
TD-
TD+
RD-
RD+
LED_SPEED/
FX_SD
GPIO1
RX_ER
CRS/CRS_DV
RX_DV
GPIO2
TXD_3
Pin Name
Pin Name
S, I/O, PU
Type
S, O, PU
S, O, PU
S, O, PD
S, I, PD
S, I, PD
S, I, PD
I/O
I/O
Type
Pin #
16
17
13
14
27
Pin #
21
41
40
39
22
6
Differential common driver transmit output (PMD Output Pair). These
differential outputs are automatically configured to either 10BASE-T or
100BASE-TX signaling.
In Auto-MDIX mode of operation, this pair can be used as the Receive
Input pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Transmit pair.
These pins require 3.3V bias for operation.
Differential receive input (PMD Input Pair). These differential inputs are
automatically configured to accept either 100BASE-TX or 10BASE-T
signaling.
In Auto-MDIX mode of operation, this pair can be used as the Transmit
Output pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Receive pair.
These pins require 3.3V bias for operation.
FIBER MODE SIGNAL DETECT: This pin provides the Signal Detect
input for 100BASE-FX mode.
CLK_OUT OUTPUT ENABLE: When high, enables clock output on
the CLK_OUT pin at power-up.
FX ENABLE: This strapping option enables 100Base-FX (Fiber)
mode. This mode is disabled by default. An external pull-down will
enable 100Base-FX mode.
LED CONFIGURATION: This strapping option determines the mode
of operation of the LED pins. Default is Mode 1. Mode 1 and Mode 2
can be controlled via the strap option. All modes are configurable via
register access.
See
MII MODE SELECT: This strapping option determines the operating
mode of the MAC Data Interface. Default operation is MII Mode with a
value of 0 due to the internal pulldown. Strapping MII_MODE high will
cause the device to be in RMII mode of operation.
PHY CONTROL FRAME ENABLE: When high, allows the DP83630
to respond to PHY Control Frames.
RMII MASTER ENABLE: When MII_MODE is strapped high, this
strapping option enables RMII Master mode, in which the DP83630
uses a 25 MHz crystal connection on X1/X2 and generates the 50 MHz
RMII reference clock. If strapped low when MII_MODE is strapped
high, default RMII operation (RMII Slave) is enabled, in which the
DP83630 uses a 50 MHz oscillator input on X1 as the RMII reference
clock. This strap option is ignored if the MII_MODE strap is low.
16
Table 3
MII_MODE
for LED Mode Selection.
0
1
Description
Description
MAC Interface Mode
MII Mode
RMII Mode