dp83630sqx National Semiconductor Corporation, dp83630sqx Datasheet - Page 28

• Manufacturer Part Number: dp83630sqx
• Description: Precision Phyter - Ieee 1588 Precision Time Protocol Transceiver
• Manufacturer: National Semiconductor Corporation

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is not available or does not provide enough throughput. Ap-
plication software may build a packet, called a PHY Control
Frame (PCF), to be passed to the PHY through the MAC
Transmit Data interface. The PHY will intercept these packets
and use them to assert writes to Management Registers as if
they occurred via the Management Interface. Multiple register
writes may be incorporated in a single frame.
The PHY Control Frame may also be used to read a register
location. The read value will be returned in a PHY Status
Frame if that function is enabled. Only a single read may be
outstanding at any time, so only one read should be included
in a single PHY Control Frame.
The PHY Control Frame block performs the following func-
tions:
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•
•
•
•
•
PHY Control Frames can be enabled through the PCF_En-
able bit in the PHY Control Frames Configuration Register
(PCFCR). PHY Control Frames can also be enabled by using
the PCF_EN strap option. For a more detailed discussion on
the use of PHY Control Frames, refer to the Software Devel-
opment Guide for the DP83630.
10.6 PHY STATUS FRAMES
The DP83630 implements a packet-based status mechanism
that allows the PHY to queue up events and pass them to the
microcontroller through the receive data interface. The pack-
et, called a PHY Status Frame, may be used to provide IEEE
1588 status for transmit packet timestamps, receive packet
timestamps, event timestamps, and trigger conditions. In ad-
dition the device can generate status messages indicating
packet buffering errors and to return data read using the PHY
Control Frame register access mechanism.
Each PHY Status Frame may include multiple status mes-
sages. The packet will be framed such that it will look like a
IEEE 1588 frame to ensure that it will get to the IEEE 1588
software stack. The PHY will provide buffering of any incom-
ing packet to allow the status packet to be passed to the MAC.
Programmable inter-frame gap and preamble length allow the
PHY to recover lost bandwidth in the case of heavy receive
traffic.
In a PHY Status Frame, status messages are not provided in
a chronological order. Instead, they are provided in the fol-
lowing order of priority:
Parse incoming transmit packets to detect PHY Control
Frames
Truncate PHY Control Frames to prevent complete frame
from reaching the transmit physical medium
Buffer up to 15 bytes of the Frame to be intercepted by the
PHY with no portion reaching physical medium
Detect commands in the PHY Control Frame and pass
them to the register block
Check CRC to detect error conditions
Report CRC and invalid command errors to the system via
register status and/or interrupt
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1.
2.
3.
4.
5.
6.
Each of the message types may be individually enabled, al-
lowing options on which functions may be delivered in a PHY
Status Frame.
Timestamps that are delivered via PHY Status Frames will not
be reflected in the corresponding status and timestamp reg-
isters nor will they generate an interrupt.
The packet format may be configured to look like a Layer 2
Ethernet frame or a UDP/IPv4 frame.
For a more detailed discussion on the use of PHY Status
Frames, refer to the Software Development Guide for the
DP83630.
11.0 Architecture
This section describes the operations within each transceiver
module, 100BASE-TX and 10BASE-T. Each operation con-
sists of several functional blocks and is described in the
following:
— 100BASE-TX Transmitter
— 100BASE-TX Receiver
— 100BASE-FX Operation
— 10BASE-T Transceiver Module
11.1 100BASE-TX TRANSMITTER
The 100BASE-TX transmitter consists of several functional
blocks which convert synchronous 4-bit nibble data, as pro-
vided by the MII, to a scrambled MLT-3 125 Mb/s serial data
stream. Because the 100BASE-TX TP-PMD is integrated, the
differential output pins, PMD Output Pair, can be directly rout-
ed to the magnetics.
The block diagram
functional block within the 100BASE-TX transmit section.
The Transmitter section consists of the following functional
blocks:
— Code-Group Encoder and Injection block
— Scrambler block (bypass option)
— NRZ to NRZI Encoder block
— Binary to MLT-3 Converter / Common Driver block
The bypass option for the functional blocks within the
100BASE-TX transmitter provides flexibility for applications
where data conversion is not always required. The DP83630
implements the 100BASE-TX transmit state machine diagram
as specified in the IEEE 802.3u Standard, Clause 24.
PHY Control Frame Read Data
Packet Buffer Error
Transmit Timestamp
Receive Timestamp
Trigger Status
Event Timestamp
inFigure 6
provides an overview of each